aboutsummaryrefslogtreecommitdiff
path: root/examples/rp
diff options
context:
space:
mode:
authorrafael <[email protected]>2024-11-09 17:19:06 +0100
committerDario Nieuwenhuis <[email protected]>2024-12-02 23:52:03 +0100
commit75382336164c8284196eb1fad057050ba735a72d (patch)
tree51e52cc29ae768fa31029e111d2fd7111a2ee9b1 /examples/rp
parentbc5e0d60b3861ca23b09dbd7fda703a47d3d60d2 (diff)
correct rp pwm dutycycle examples: desired frequency
Diffstat (limited to 'examples/rp')
-rw-r--r--examples/rp/src/bin/pwm.rs12
1 files changed, 8 insertions, 4 deletions
diff --git a/examples/rp/src/bin/pwm.rs b/examples/rp/src/bin/pwm.rs
index 791b88b5b..06b9313f2 100644
--- a/examples/rp/src/bin/pwm.rs
+++ b/examples/rp/src/bin/pwm.rs
@@ -48,11 +48,15 @@ async fn pwm_set_dutycycle(slice2: PWM_SLICE2, pin4: PIN_4) {
48 // If we aim for a specific frequency, here is how we can calculate the top value. 48 // If we aim for a specific frequency, here is how we can calculate the top value.
49 // The top value sets the period of the PWM cycle, so a counter goes from 0 to top and then wraps around to 0. 49 // The top value sets the period of the PWM cycle, so a counter goes from 0 to top and then wraps around to 0.
50 // Every such wraparound is one PWM cycle. So here is how we get 25KHz: 50 // Every such wraparound is one PWM cycle. So here is how we get 25KHz:
51 let desired_freq_hz = 25_000;
52 let clock_freq_hz = embassy_rp::clocks::clk_sys_freq();
53 let divider = 16u8;
54 let period = (clock_freq_hz / (desired_freq_hz * divider as u32)) as u16 - 1;
55
51 let mut c = Config::default(); 56 let mut c = Config::default();
52 let pwm_freq = 25_000; // Hz, our desired frequency 57 c.top = period;
53 let clock_freq = embassy_rp::clocks::clk_sys_freq(); 58 c.divider = divider.into();
54 c.top = (clock_freq / pwm_freq) as u16 - 1; 59
55
56 let mut pwm = Pwm::new_output_a(slice2, pin4, c.clone()); 60 let mut pwm = Pwm::new_output_a(slice2, pin4, c.clone());
57 61
58 loop { 62 loop {