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| author | bors[bot] <26634292+bors[bot]@users.noreply.github.com> | 2023-05-04 20:04:11 +0000 |
|---|---|---|
| committer | GitHub <[email protected]> | 2023-05-04 20:04:11 +0000 |
| commit | 067f1382e4d23d25a2554926b2077ae7c0b5f8d1 (patch) | |
| tree | 924e0294a5066cff0e1c012b66fb709a308f33bf /examples/std/src/bin | |
| parent | 72e36d89974f57999525ae277a462e162ce1b283 (diff) | |
| parent | c44c108db57cbe34e21411054840f61c61efa8a8 (diff) | |
Merge #1429
1429: rp pio, √9 r=Dirbaio a=pennae
another mix of refactoring and soundness issues. most notably pio pins are now checked for being actually accessible to the pio blocks, are constructible from not just the owned peripherals but refs as well, and have their registrations to the pio block reverted once all state machines and the common block has been dropped.
state machines are now also stopped when dropped, and concurrent rx+tx using dma can finally be done in a sound manner. previously it was possible to do, but allowed users to start two concurrent transfers to the same fifo using different dma channels, which obviously would not have the expected results on average.
Co-authored-by: pennae <[email protected]>
Diffstat (limited to 'examples/std/src/bin')
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