diff options
| author | xoviat <[email protected]> | 2023-09-16 17:41:11 -0500 |
|---|---|---|
| committer | xoviat <[email protected]> | 2023-09-16 17:41:11 -0500 |
| commit | de2773afdd3f2d06cad0632ee075e1b88aa71515 (patch) | |
| tree | 6782dfb9aec3b5ba87f6e68eedf8910d4ead3869 /examples/stm32f2/src/bin/pll.rs | |
| parent | 044b837caaa90ce4a52a2f2f5be8a657e6ff61a7 (diff) | |
stm32/rcc: convert bus prescalers to pac enums
Diffstat (limited to 'examples/stm32f2/src/bin/pll.rs')
| -rw-r--r-- | examples/stm32f2/src/bin/pll.rs | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/examples/stm32f2/src/bin/pll.rs b/examples/stm32f2/src/bin/pll.rs index 17f09538c..894937614 100644 --- a/examples/stm32f2/src/bin/pll.rs +++ b/examples/stm32f2/src/bin/pll.rs | |||
| @@ -39,9 +39,9 @@ async fn main(_spawner: Spawner) { | |||
| 39 | // System clock comes from PLL (= the 120 MHz main PLL output) | 39 | // System clock comes from PLL (= the 120 MHz main PLL output) |
| 40 | config.rcc.mux = ClockSrc::PLL; | 40 | config.rcc.mux = ClockSrc::PLL; |
| 41 | // 120 MHz / 4 = 30 MHz APB1 frequency | 41 | // 120 MHz / 4 = 30 MHz APB1 frequency |
| 42 | config.rcc.apb1_pre = APBPrescaler::Div4; | 42 | config.rcc.apb1_pre = APBPrescaler::DIV4; |
| 43 | // 120 MHz / 2 = 60 MHz APB2 frequency | 43 | // 120 MHz / 2 = 60 MHz APB2 frequency |
| 44 | config.rcc.apb2_pre = APBPrescaler::Div2; | 44 | config.rcc.apb2_pre = APBPrescaler::DIV2; |
| 45 | 45 | ||
| 46 | let _p = embassy_stm32::init(config); | 46 | let _p = embassy_stm32::init(config); |
| 47 | 47 | ||