Enable DMA for SPIv1 on F4's etc.

4 files changed, 92 insertions, 3 deletions

diff --git a/examples/stm32f4/.cargo/config.toml b/examples/stm32f4/.cargo/config.toml
index 8704a9ba5..f7173a194 100644
--- a/examples/stm32f4/.cargo/config.toml
+++ b/examples/stm32f4/.cargo/config.toml
@@ -3,7 +3,8 @@ build-std = ["core"]
 
 [target.'cfg(all(target_arch = "arm", target_os = "none"))']
 # replace STM32F429ZITx with your chip as listed in `probe-run --list-chips`
-runner = "probe-run --chip STM32F429ZITx"
+#runner = "probe-run --chip STM32F429ZITx"
+runner = "probe-run --chip STM32F401RE"
 
 rustflags = [
   # LLD (shipped with the Rust toolchain) is used as the default linker
diff --git a/examples/stm32f4/memory.x b/examples/stm32f4/memory.x
index f21e32572..bcd2bbcd4 100644
--- a/examples/stm32f4/memory.x
+++ b/examples/stm32f4/memory.x
@@ -2,6 +2,6 @@ MEMORY
 {
   /* NOTE 1 K = 1 KiBi = 1024 bytes */
   /* These values correspond to the STM32F429ZI */
-  FLASH : ORIGIN = 0x08000000, LENGTH = 2048K
-  RAM : ORIGIN = 0x20000000, LENGTH = 192K
+  FLASH : ORIGIN = 0x08000000, LENGTH = 512K
+  RAM : ORIGIN = 0x20000000, LENGTH = 96K
 }
diff --git a/examples/stm32f4/src/bin/spi.rs b/examples/stm32f4/src/bin/spi.rs
index 88fc84bc0..604283877 100644
--- a/examples/stm32f4/src/bin/spi.rs
+++ b/examples/stm32f4/src/bin/spi.rs
@@ -18,6 +18,7 @@ use embassy_stm32::dbgmcu::Dbgmcu;
 use embassy_stm32::spi::{Config, Spi};
 use embassy_stm32::time::Hertz;
 use embedded_hal::blocking::spi::Transfer;
+use embassy_stm32::dma::NoDma;
 
 #[entry]
 fn main() -> ! {
@@ -34,6 +35,8 @@ fn main() -> ! {
         p.PC10,
         p.PC12,
         p.PC11,
+        NoDma,
+        NoDma,
         Hertz(1_000_000),
         Config::default(),
     );
diff --git a/examples/stm32f4/src/bin/spi_dma.rs b/examples/stm32f4/src/bin/spi_dma.rs
new file mode 100644
index 000000000..db6b69c85
--- /dev/null
+++ b/examples/stm32f4/src/bin/spi_dma.rs
@@ -0,0 +1,85 @@
+#![no_std]
+#![no_main]
+#![feature(trait_alias)]
+#![feature(min_type_alias_impl_trait)]
+#![feature(impl_trait_in_bindings)]
+#![feature(type_alias_impl_trait)]
+#![allow(incomplete_features)]
+
+#[path = "../example_common.rs"]
+mod example_common;
+use core::fmt::Write;
+use cortex_m_rt::entry;
+use embassy::executor::Executor;
+use embassy::time::Clock;
+use embassy::util::Forever;
+use example_common::*;
+use embassy_traits::spi::FullDuplex;
+use heapless::String;
+use embassy_stm32::spi::{Spi, Config};
+use embassy_stm32::pac;
+use embassy_stm32::time::Hertz;
+use core::str::from_utf8;
+
+#[embassy::task]
+async fn main_task() {
+    let p = embassy_stm32::init(Default::default());
+
+    let mut spi = Spi::new(
+        p.SPI1,
+        p.PB3,
+        p.PA7,
+        p.PA6,
+        p.DMA2_CH3,
+        p.DMA2_CH2,
+        Hertz(1_000_000),
+        Config::default(),
+    );
+
+    for n in 0u32.. {
+        let mut write: String<128> = String::new();
+        let mut read = [0;128];
+        core::write!(&mut write, "Hello DMA World {}!\r\n", n).unwrap();
+        spi.read_write(&mut read[0..write.len()], write.as_bytes()).await.ok();
+        info!("read via spi+dma: {}", from_utf8(&read).unwrap());
+    }
+}
+
+struct ZeroClock;
+
+impl Clock for ZeroClock {
+    fn now(&self) -> u64 {
+        0
+    }
+}
+
+static EXECUTOR: Forever<Executor> = Forever::new();
+
+#[entry]
+fn main() -> ! {
+    info!("Hello World!");
+    unsafe {
+        pac::DBGMCU.cr().modify(|w| {
+            w.set_dbg_sleep(true);
+            w.set_dbg_standby(true);
+            w.set_dbg_stop(true);
+        });
+
+        pac::RCC.ahb1enr().modify(|w| {
+            w.set_gpioaen(true);
+            w.set_gpioben(true);
+            w.set_gpiocen(true);
+            w.set_gpioden(true);
+            w.set_gpioeen(true);
+            w.set_gpiofen(true);
+        });
+    }
+
+    unsafe { embassy::time::set_clock(&ZeroClock) };
+
+    let executor = EXECUTOR.put(Executor::new());
+
+    executor.run(|spawner| {
+        unwrap!(spawner.spawn(main_task()));
+    })
+}