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| author | vinsynth <[email protected]> | 2025-02-03 22:52:38 -0500 |
|---|---|---|
| committer | vinsynth <[email protected]> | 2025-02-03 22:52:38 -0500 |
| commit | b0e3a6481b5bacadc3d538f571d21f96b274934e (patch) | |
| tree | fc9841be1b254a8515171269179ee13862696d05 /examples/stm32f4 | |
| parent | b5a635371434f4b71554d841ca8bb66ce824578f (diff) | |
document clock settings in examples/stm32f4/.../i2s_dma.rs
Diffstat (limited to 'examples/stm32f4')
| -rw-r--r-- | examples/stm32f4/src/bin/i2s_dma.rs | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/examples/stm32f4/src/bin/i2s_dma.rs b/examples/stm32f4/src/bin/i2s_dma.rs index 618717cc9..db5103d0f 100644 --- a/examples/stm32f4/src/bin/i2s_dma.rs +++ b/examples/stm32f4/src/bin/i2s_dma.rs | |||
| @@ -36,6 +36,8 @@ async fn main(_spawner: Spawner) { | |||
| 36 | config.rcc.apb1_pre = APBPrescaler::DIV2; | 36 | config.rcc.apb1_pre = APBPrescaler::DIV2; |
| 37 | config.rcc.apb2_pre = APBPrescaler::DIV1; | 37 | config.rcc.apb2_pre = APBPrescaler::DIV1; |
| 38 | 38 | ||
| 39 | // reference your chip's manual for proper clock settings; this config | ||
| 40 | // is recommended for a 32 bit frame at 48 kHz sample rate | ||
| 39 | config.rcc.plli2s = Some(Pll { | 41 | config.rcc.plli2s = Some(Pll { |
| 40 | prediv: PllPreDiv::DIV25, | 42 | prediv: PllPreDiv::DIV25, |
| 41 | mul: PllMul::MUL384, | 43 | mul: PllMul::MUL384, |