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authorPiotr Esden-Tempski <[email protected]>2024-12-17 14:56:45 -0800
committerPiotr Esden-Tempski <[email protected]>2024-12-17 14:56:45 -0800
commitbafcdedebe1b94a9eb35a397553ee9ecab237080 (patch)
tree47e7659bd47c28f4c08eece5eeda08b137e49a47 /examples/stm32f7
parentb2e82684707e8675f61bba01e818947ba536d3c7 (diff)
Update (q|o)spi examples.
Diffstat (limited to 'examples/stm32f7')
-rw-r--r--examples/stm32f7/src/bin/qspi.rs4
1 files changed, 2 insertions, 2 deletions
diff --git a/examples/stm32f7/src/bin/qspi.rs b/examples/stm32f7/src/bin/qspi.rs
index 90d319b7a..bd3287964 100644
--- a/examples/stm32f7/src/bin/qspi.rs
+++ b/examples/stm32f7/src/bin/qspi.rs
@@ -72,7 +72,7 @@ impl<I: Instance> FlashMemory<I> {
72 address: None, 72 address: None,
73 dummy: DummyCycles::_0, 73 dummy: DummyCycles::_0,
74 }; 74 };
75 self.qspi.command(transaction); 75 self.qspi.blocking_command(transaction);
76 } 76 }
77 77
78 pub fn reset_memory(&mut self) { 78 pub fn reset_memory(&mut self) {
@@ -143,7 +143,7 @@ impl<I: Instance> FlashMemory<I> {
143 dummy: DummyCycles::_0, 143 dummy: DummyCycles::_0,
144 }; 144 };
145 self.enable_write(); 145 self.enable_write();
146 self.qspi.command(transaction); 146 self.qspi.blocking_command(transaction);
147 self.wait_write_finish(); 147 self.wait_write_finish();
148 } 148 }
149 149