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authorDario Nieuwenhuis <[email protected]>2023-11-13 00:52:01 +0100
committerDario Nieuwenhuis <[email protected]>2023-11-13 00:52:01 +0100
commit4fe344ebc0f4e030ff7a03755f27e66e9ad0476f (patch)
treef4c40f8f346d52f2180ccf39f2d811337a2e9621 /examples/stm32g4/src/bin/usb_serial.rs
parent39c737162185adb4f30f18f700da08a55be6b55a (diff)
stm32/rcc: consistent casing and naming for PLL enums.
Diffstat (limited to 'examples/stm32g4/src/bin/usb_serial.rs')
-rw-r--r--examples/stm32g4/src/bin/usb_serial.rs8
1 files changed, 4 insertions, 4 deletions
diff --git a/examples/stm32g4/src/bin/usb_serial.rs b/examples/stm32g4/src/bin/usb_serial.rs
index 378e7b988..565b25d60 100644
--- a/examples/stm32g4/src/bin/usb_serial.rs
+++ b/examples/stm32g4/src/bin/usb_serial.rs
@@ -4,7 +4,7 @@
4 4
5use defmt::{panic, *}; 5use defmt::{panic, *};
6use embassy_executor::Spawner; 6use embassy_executor::Spawner;
7use embassy_stm32::rcc::{Clock48MhzSrc, ClockSrc, Hsi48Config, Pll, PllM, PllN, PllQ, PllR, PllSrc}; 7use embassy_stm32::rcc::{Clock48MhzSrc, ClockSrc, Hsi48Config, Pll, PllM, PllN, PllQ, PllR, PllSource};
8use embassy_stm32::time::Hertz; 8use embassy_stm32::time::Hertz;
9use embassy_stm32::usb::{self, Driver, Instance}; 9use embassy_stm32::usb::{self, Driver, Instance};
10use embassy_stm32::{bind_interrupts, peripherals, Config}; 10use embassy_stm32::{bind_interrupts, peripherals, Config};
@@ -25,14 +25,14 @@ async fn main(_spawner: Spawner) {
25 // Change this to `false` to use the HSE clock source for the USB. This example assumes an 8MHz HSE. 25 // Change this to `false` to use the HSE clock source for the USB. This example assumes an 8MHz HSE.
26 const USE_HSI48: bool = true; 26 const USE_HSI48: bool = true;
27 27
28 let pllq_div = if USE_HSI48 { None } else { Some(PllQ::DIV6) }; 28 let plldivq = if USE_HSI48 { None } else { Some(PllQ::DIV6) };
29 29
30 config.rcc.pll = Some(Pll { 30 config.rcc.pll = Some(Pll {
31 source: PllSrc::HSE(Hertz(8_000_000)), 31 source: PllSource::HSE(Hertz(8_000_000)),
32 prediv_m: PllM::DIV2, 32 prediv_m: PllM::DIV2,
33 mul_n: PllN::MUL72, 33 mul_n: PllN::MUL72,
34 div_p: None, 34 div_p: None,
35 div_q: pllq_div, 35 div_q: plldivq,
36 // Main system clock at 144 MHz 36 // Main system clock at 144 MHz
37 div_r: Some(PllR::DIV2), 37 div_r: Some(PllR::DIV2),
38 }); 38 });