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authorBarnaby Walters <[email protected]>2024-02-15 23:56:26 +0100
committerBarnaby Walters <[email protected]>2024-02-15 23:56:26 +0100
commit5b7eff65417e491fa7908dfd8b62013efb55d30b (patch)
treedb30781f8c7fc217578ed288c0594c1f23ff6354 /examples/stm32g4/src/bin/usb_serial.rs
parente8c998aad882d766988ac2c0cb0c357c600b28c1 (diff)
[embassy-stm32]: started stm32g4 RCC refactor
* Copied API from f.rs where applicable * HSE and HSI independantly configurable * Boost mode set by user rather * Added HSE, pll1_q and pll1_p frequencies to set_clocks call * Stubbed max module based on f.rs, needs cleanup
Diffstat (limited to 'examples/stm32g4/src/bin/usb_serial.rs')
-rw-r--r--examples/stm32g4/src/bin/usb_serial.rs29
1 files changed, 18 insertions, 11 deletions
diff --git a/examples/stm32g4/src/bin/usb_serial.rs b/examples/stm32g4/src/bin/usb_serial.rs
index c26fa76b7..d9207e4cd 100644
--- a/examples/stm32g4/src/bin/usb_serial.rs
+++ b/examples/stm32g4/src/bin/usb_serial.rs
@@ -3,7 +3,9 @@
3 3
4use defmt::{panic, *}; 4use defmt::{panic, *};
5use embassy_executor::Spawner; 5use embassy_executor::Spawner;
6use embassy_stm32::rcc::{Clock48MhzSrc, ClockSrc, Hsi48Config, Pll, PllM, PllN, PllQ, PllR, PllSource}; 6use embassy_stm32::rcc::{
7 Clock48MhzSrc, Hse, HseMode, Hsi48Config, Pll, PllMul, PllPreDiv, PllQDiv, PllRDiv, Pllsrc, Sysclk,
8};
7use embassy_stm32::time::Hertz; 9use embassy_stm32::time::Hertz;
8use embassy_stm32::usb::{self, Driver, Instance}; 10use embassy_stm32::usb::{self, Driver, Instance};
9use embassy_stm32::{bind_interrupts, peripherals, Config}; 11use embassy_stm32::{bind_interrupts, peripherals, Config};
@@ -24,25 +26,30 @@ async fn main(_spawner: Spawner) {
24 // Change this to `false` to use the HSE clock source for the USB. This example assumes an 8MHz HSE. 26 // Change this to `false` to use the HSE clock source for the USB. This example assumes an 8MHz HSE.
25 const USE_HSI48: bool = true; 27 const USE_HSI48: bool = true;
26 28
27 let plldivq = if USE_HSI48 { None } else { Some(PllQ::DIV6) }; 29 let plldivq = if USE_HSI48 { None } else { Some(PllQDiv::DIV6) };
30
31 config.rcc.hse = Some(Hse {
32 freq: Hertz(8_000_000),
33 mode: HseMode::Oscillator,
34 });
28 35
29 config.rcc.pll = Some(Pll { 36 config.rcc.pll = Some(Pll {
30 source: PllSource::HSE(Hertz(8_000_000)), 37 source: Pllsrc::HSE,
31 prediv_m: PllM::DIV2, 38 prediv: PllPreDiv::DIV2,
32 mul_n: PllN::MUL72, 39 mul: PllMul::MUL72,
33 div_p: None, 40 divp: None,
34 div_q: plldivq, 41 divq: plldivq,
35 // Main system clock at 144 MHz 42 // Main system clock at 144 MHz
36 div_r: Some(PllR::DIV2), 43 divr: Some(PllRDiv::DIV2),
37 }); 44 });
38 45
39 config.rcc.mux = ClockSrc::PLL; 46 config.rcc.sys = Sysclk::PLL1_R;
40 47
41 if USE_HSI48 { 48 if USE_HSI48 {
42 // Sets up the Clock Recovery System (CRS) to use the USB SOF to trim the HSI48 oscillator. 49 // Sets up the Clock Recovery System (CRS) to use the USB SOF to trim the HSI48 oscillator.
43 config.rcc.clock_48mhz_src = Some(Clock48MhzSrc::Hsi48(Hsi48Config { sync_from_usb: true })); 50 config.rcc.clk48_src = Some(Clock48MhzSrc::Hsi48(Hsi48Config { sync_from_usb: true }));
44 } else { 51 } else {
45 config.rcc.clock_48mhz_src = Some(Clock48MhzSrc::PllQ); 52 config.rcc.clk48_src = Some(Clock48MhzSrc::PllQ);
46 } 53 }
47 54
48 let p = embassy_stm32::init(config); 55 let p = embassy_stm32::init(config);