diff options
| author | xoviat <[email protected]> | 2025-11-05 14:15:25 -0600 |
|---|---|---|
| committer | xoviat <[email protected]> | 2025-11-05 14:15:25 -0600 |
| commit | 338c5bfc96c2b575a3e4007c23359a49c85fae00 (patch) | |
| tree | 5bf36906c26886641e611485b67e29eb7fdb0288 /examples/stm32g4 | |
| parent | 8f6ce6b13e9ed1707f945d276439a31420f28bfb (diff) | |
consume regular ringbuf
Diffstat (limited to 'examples/stm32g4')
| -rw-r--r-- | examples/stm32g4/src/bin/adc_injected_and_regular.rs | 18 |
1 files changed, 12 insertions, 6 deletions
diff --git a/examples/stm32g4/src/bin/adc_injected_and_regular.rs b/examples/stm32g4/src/bin/adc_injected_and_regular.rs index 85e01dbf3..d0c577b4b 100644 --- a/examples/stm32g4/src/bin/adc_injected_and_regular.rs +++ b/examples/stm32g4/src/bin/adc_injected_and_regular.rs | |||
| @@ -9,7 +9,8 @@ | |||
| 9 | use core::cell::RefCell; | 9 | use core::cell::RefCell; |
| 10 | 10 | ||
| 11 | use defmt::info; | 11 | use defmt::info; |
| 12 | use embassy_stm32::adc::{Adc, AdcChannel as _, Exten, SampleTime, ConversionTrigger, RegularConversionMode}; | 12 | use embassy_stm32::adc::InjectedAdc; |
| 13 | use embassy_stm32::adc::{Adc, AdcChannel as _, ConversionTrigger, Exten, RegularConversionMode, SampleTime}; | ||
| 13 | use embassy_stm32::interrupt::typelevel::{ADC1_2, Interrupt}; | 14 | use embassy_stm32::interrupt::typelevel::{ADC1_2, Interrupt}; |
| 14 | use embassy_stm32::peripherals::ADC1; | 15 | use embassy_stm32::peripherals::ADC1; |
| 15 | use embassy_stm32::time::Hertz; | 16 | use embassy_stm32::time::Hertz; |
| @@ -17,7 +18,6 @@ use embassy_stm32::timer::complementary_pwm::{ComplementaryPwm, Mms2}; | |||
| 17 | use embassy_stm32::timer::low_level::CountingMode; | 18 | use embassy_stm32::timer::low_level::CountingMode; |
| 18 | use embassy_stm32::{Config, interrupt}; | 19 | use embassy_stm32::{Config, interrupt}; |
| 19 | use embassy_sync::blocking_mutex::CriticalSectionMutex; | 20 | use embassy_sync::blocking_mutex::CriticalSectionMutex; |
| 20 | use embassy_stm32::adc::InjectedAdc; | ||
| 21 | use {critical_section, defmt_rtt as _, panic_probe as _}; | 21 | use {critical_section, defmt_rtt as _, panic_probe as _}; |
| 22 | 22 | ||
| 23 | static ADC1_HANDLE: CriticalSectionMutex<RefCell<Option<InjectedAdc<ADC1>>>> = | 23 | static ADC1_HANDLE: CriticalSectionMutex<RefCell<Option<InjectedAdc<ADC1>>>> = |
| @@ -76,7 +76,7 @@ async fn main(_spawner: embassy_executor::Spawner) { | |||
| 76 | pwm.set_mms2(Mms2::UPDATE); | 76 | pwm.set_mms2(Mms2::UPDATE); |
| 77 | 77 | ||
| 78 | // Configure regular conversions with DMA | 78 | // Configure regular conversions with DMA |
| 79 | let mut adc1 = Adc::new(p.ADC1); | 79 | let adc1 = Adc::new(p.ADC1); |
| 80 | 80 | ||
| 81 | let mut vrefint_channel = adc1.enable_vrefint().degrade_adc(); | 81 | let mut vrefint_channel = adc1.enable_vrefint().degrade_adc(); |
| 82 | let mut pa0 = p.PC1.degrade_adc(); | 82 | let mut pa0 = p.PC1.degrade_adc(); |
| @@ -95,10 +95,16 @@ async fn main(_spawner: embassy_executor::Spawner) { | |||
| 95 | // Using buffer of double size means the half-full interrupts will generate at the expected rate | 95 | // Using buffer of double size means the half-full interrupts will generate at the expected rate |
| 96 | let mut readings = [0u16; 4]; | 96 | let mut readings = [0u16; 4]; |
| 97 | 97 | ||
| 98 | let injected_trigger = ConversionTrigger { channel: ADC1_INJECTED_TRIGGER_TIM1_TRGO2, edge: Exten::RISING_EDGE }; | 98 | let injected_trigger = ConversionTrigger { |
| 99 | let regular_trigger = ConversionTrigger { channel: ADC1_REGULAR_TRIGGER_TIM1_TRGO2, edge: Exten::RISING_EDGE }; | 99 | channel: ADC1_INJECTED_TRIGGER_TIM1_TRGO2, |
| 100 | edge: Exten::RISING_EDGE, | ||
| 101 | }; | ||
| 102 | let regular_trigger = ConversionTrigger { | ||
| 103 | channel: ADC1_REGULAR_TRIGGER_TIM1_TRGO2, | ||
| 104 | edge: Exten::RISING_EDGE, | ||
| 105 | }; | ||
| 100 | 106 | ||
| 101 | let (mut ring_buffered_adc, injected_adc) = adc1.into_regular_ringbuffered_and_injected_interrupts( | 107 | let (mut ring_buffered_adc, injected_adc) = adc1.into_ring_buffered_and_injected( |
| 102 | dma1_ch1, | 108 | dma1_ch1, |
| 103 | &mut readings, | 109 | &mut readings, |
| 104 | regular_sequence, | 110 | regular_sequence, |
