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authorDario Nieuwenhuis <[email protected]>2023-11-05 23:35:01 +0100
committerDario Nieuwenhuis <[email protected]>2023-11-05 23:52:54 +0100
commit0272deb158c4cc821e8f587283817a0fe5f82cf8 (patch)
tree9774d81020c3da632e676017d471b1d2d06aae2e /examples/stm32h5/src/bin/eth.rs
parentc4a8b79dbc927e46fcc71879673ad3410aa3174b (diff)
stm32/rcc: add shared code for hsi48 with crs support.
Diffstat (limited to 'examples/stm32h5/src/bin/eth.rs')
-rw-r--r--examples/stm32h5/src/bin/eth.rs2
1 files changed, 1 insertions, 1 deletions
diff --git a/examples/stm32h5/src/bin/eth.rs b/examples/stm32h5/src/bin/eth.rs
index 5bec9d447..b2758cba0 100644
--- a/examples/stm32h5/src/bin/eth.rs
+++ b/examples/stm32h5/src/bin/eth.rs
@@ -37,7 +37,7 @@ async fn net_task(stack: &'static Stack<Device>) -> ! {
37async fn main(spawner: Spawner) -> ! { 37async fn main(spawner: Spawner) -> ! {
38 let mut config = Config::default(); 38 let mut config = Config::default();
39 config.rcc.hsi = None; 39 config.rcc.hsi = None;
40 config.rcc.hsi48 = true; // needed for rng 40 config.rcc.hsi48 = Some(Default::default()); // needed for RNG
41 config.rcc.hse = Some(Hse { 41 config.rcc.hse = Some(Hse {
42 freq: Hertz(8_000_000), 42 freq: Hertz(8_000_000),
43 mode: HseMode::BypassDigital, 43 mode: HseMode::BypassDigital,