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authorDario Nieuwenhuis <[email protected]>2023-10-23 01:48:09 +0200
committerDario Nieuwenhuis <[email protected]>2023-10-23 17:36:21 +0200
commita39ae12edcf23935df82d547fb2d997ca6b7c8d5 (patch)
treed13df6dec747ab5d3af23c7dac1b12c085b26cfd /examples/stm32h5
parent0ef1cb29f70c71d3c85f5b8b4ad3c7ce60babba8 (diff)
stm32/rcc: misc cleanups.
Diffstat (limited to 'examples/stm32h5')
-rw-r--r--examples/stm32h5/src/bin/eth.rs4
-rw-r--r--examples/stm32h5/src/bin/usb_serial.rs4
2 files changed, 4 insertions, 4 deletions
diff --git a/examples/stm32h5/src/bin/eth.rs b/examples/stm32h5/src/bin/eth.rs
index 6e40f0ac0..5bec9d447 100644
--- a/examples/stm32h5/src/bin/eth.rs
+++ b/examples/stm32h5/src/bin/eth.rs
@@ -43,7 +43,7 @@ async fn main(spawner: Spawner) -> ! {
43 mode: HseMode::BypassDigital, 43 mode: HseMode::BypassDigital,
44 }); 44 });
45 config.rcc.pll1 = Some(Pll { 45 config.rcc.pll1 = Some(Pll {
46 source: PllSource::Hse, 46 source: PllSource::HSE,
47 prediv: PllPreDiv::DIV2, 47 prediv: PllPreDiv::DIV2,
48 mul: PllMul::MUL125, 48 mul: PllMul::MUL125,
49 divp: Some(PllDiv::DIV2), 49 divp: Some(PllDiv::DIV2),
@@ -54,7 +54,7 @@ async fn main(spawner: Spawner) -> ! {
54 config.rcc.apb1_pre = APBPrescaler::DIV1; 54 config.rcc.apb1_pre = APBPrescaler::DIV1;
55 config.rcc.apb2_pre = APBPrescaler::DIV1; 55 config.rcc.apb2_pre = APBPrescaler::DIV1;
56 config.rcc.apb3_pre = APBPrescaler::DIV1; 56 config.rcc.apb3_pre = APBPrescaler::DIV1;
57 config.rcc.sys = Sysclk::Pll1P; 57 config.rcc.sys = Sysclk::PLL1_P;
58 config.rcc.voltage_scale = VoltageScale::Scale0; 58 config.rcc.voltage_scale = VoltageScale::Scale0;
59 let p = embassy_stm32::init(config); 59 let p = embassy_stm32::init(config);
60 info!("Hello World!"); 60 info!("Hello World!");
diff --git a/examples/stm32h5/src/bin/usb_serial.rs b/examples/stm32h5/src/bin/usb_serial.rs
index 3b3c38e17..735826a69 100644
--- a/examples/stm32h5/src/bin/usb_serial.rs
+++ b/examples/stm32h5/src/bin/usb_serial.rs
@@ -30,7 +30,7 @@ async fn main(_spawner: Spawner) {
30 mode: HseMode::BypassDigital, 30 mode: HseMode::BypassDigital,
31 }); 31 });
32 config.rcc.pll1 = Some(Pll { 32 config.rcc.pll1 = Some(Pll {
33 source: PllSource::Hse, 33 source: PllSource::HSE,
34 prediv: PllPreDiv::DIV2, 34 prediv: PllPreDiv::DIV2,
35 mul: PllMul::MUL125, 35 mul: PllMul::MUL125,
36 divp: Some(PllDiv::DIV2), // 250mhz 36 divp: Some(PllDiv::DIV2), // 250mhz
@@ -41,7 +41,7 @@ async fn main(_spawner: Spawner) {
41 config.rcc.apb1_pre = APBPrescaler::DIV4; 41 config.rcc.apb1_pre = APBPrescaler::DIV4;
42 config.rcc.apb2_pre = APBPrescaler::DIV2; 42 config.rcc.apb2_pre = APBPrescaler::DIV2;
43 config.rcc.apb3_pre = APBPrescaler::DIV4; 43 config.rcc.apb3_pre = APBPrescaler::DIV4;
44 config.rcc.sys = Sysclk::Pll1P; 44 config.rcc.sys = Sysclk::PLL1_P;
45 config.rcc.voltage_scale = VoltageScale::Scale0; 45 config.rcc.voltage_scale = VoltageScale::Scale0;
46 let p = embassy_stm32::init(config); 46 let p = embassy_stm32::init(config);
47 47