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authorDario Nieuwenhuis <[email protected]>2023-11-05 23:35:01 +0100
committerDario Nieuwenhuis <[email protected]>2023-11-05 23:52:54 +0100
commit0272deb158c4cc821e8f587283817a0fe5f82cf8 (patch)
tree9774d81020c3da632e676017d471b1d2d06aae2e /examples/stm32h7/src/bin/eth_client.rs
parentc4a8b79dbc927e46fcc71879673ad3410aa3174b (diff)
stm32/rcc: add shared code for hsi48 with crs support.
Diffstat (limited to 'examples/stm32h7/src/bin/eth_client.rs')
-rw-r--r--examples/stm32h7/src/bin/eth_client.rs2
1 files changed, 1 insertions, 1 deletions
diff --git a/examples/stm32h7/src/bin/eth_client.rs b/examples/stm32h7/src/bin/eth_client.rs
index 88df53f01..f0f28ec9c 100644
--- a/examples/stm32h7/src/bin/eth_client.rs
+++ b/examples/stm32h7/src/bin/eth_client.rs
@@ -37,7 +37,7 @@ async fn main(spawner: Spawner) -> ! {
37 use embassy_stm32::rcc::*; 37 use embassy_stm32::rcc::*;
38 config.rcc.hsi = Some(HSIPrescaler::DIV1); 38 config.rcc.hsi = Some(HSIPrescaler::DIV1);
39 config.rcc.csi = true; 39 config.rcc.csi = true;
40 config.rcc.hsi48 = true; // needed for RNG 40 config.rcc.hsi48 = Some(Default::default()); // needed for RNG
41 config.rcc.pll1 = Some(Pll { 41 config.rcc.pll1 = Some(Pll {
42 source: PllSource::HSI, 42 source: PllSource::HSI,
43 prediv: PllPreDiv::DIV4, 43 prediv: PllPreDiv::DIV4,