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authorDario Nieuwenhuis <[email protected]>2023-10-23 01:48:09 +0200
committerDario Nieuwenhuis <[email protected]>2023-10-23 17:36:21 +0200
commita39ae12edcf23935df82d547fb2d997ca6b7c8d5 (patch)
treed13df6dec747ab5d3af23c7dac1b12c085b26cfd /examples/stm32h7/src/bin/eth_client.rs
parent0ef1cb29f70c71d3c85f5b8b4ad3c7ce60babba8 (diff)
stm32/rcc: misc cleanups.
Diffstat (limited to 'examples/stm32h7/src/bin/eth_client.rs')
-rw-r--r--examples/stm32h7/src/bin/eth_client.rs6
1 files changed, 3 insertions, 3 deletions
diff --git a/examples/stm32h7/src/bin/eth_client.rs b/examples/stm32h7/src/bin/eth_client.rs
index 338137069..88df53f01 100644
--- a/examples/stm32h7/src/bin/eth_client.rs
+++ b/examples/stm32h7/src/bin/eth_client.rs
@@ -35,18 +35,18 @@ async fn main(spawner: Spawner) -> ! {
35 let mut config = Config::default(); 35 let mut config = Config::default();
36 { 36 {
37 use embassy_stm32::rcc::*; 37 use embassy_stm32::rcc::*;
38 config.rcc.hsi = Some(Hsi::Mhz64); 38 config.rcc.hsi = Some(HSIPrescaler::DIV1);
39 config.rcc.csi = true; 39 config.rcc.csi = true;
40 config.rcc.hsi48 = true; // needed for RNG 40 config.rcc.hsi48 = true; // needed for RNG
41 config.rcc.pll_src = PllSource::Hsi;
42 config.rcc.pll1 = Some(Pll { 41 config.rcc.pll1 = Some(Pll {
42 source: PllSource::HSI,
43 prediv: PllPreDiv::DIV4, 43 prediv: PllPreDiv::DIV4,
44 mul: PllMul::MUL50, 44 mul: PllMul::MUL50,
45 divp: Some(PllDiv::DIV2), 45 divp: Some(PllDiv::DIV2),
46 divq: None, 46 divq: None,
47 divr: None, 47 divr: None,
48 }); 48 });
49 config.rcc.sys = Sysclk::Pll1P; // 400 Mhz 49 config.rcc.sys = Sysclk::PLL1_P; // 400 Mhz
50 config.rcc.ahb_pre = AHBPrescaler::DIV2; // 200 Mhz 50 config.rcc.ahb_pre = AHBPrescaler::DIV2; // 200 Mhz
51 config.rcc.apb1_pre = APBPrescaler::DIV2; // 100 Mhz 51 config.rcc.apb1_pre = APBPrescaler::DIV2; // 100 Mhz
52 config.rcc.apb2_pre = APBPrescaler::DIV2; // 100 Mhz 52 config.rcc.apb2_pre = APBPrescaler::DIV2; // 100 Mhz