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authorDario Nieuwenhuis <[email protected]>2023-10-23 01:48:09 +0200
committerDario Nieuwenhuis <[email protected]>2023-10-23 17:36:21 +0200
commita39ae12edcf23935df82d547fb2d997ca6b7c8d5 (patch)
treed13df6dec747ab5d3af23c7dac1b12c085b26cfd /examples/stm32h7/src/bin/fmc.rs
parent0ef1cb29f70c71d3c85f5b8b4ad3c7ce60babba8 (diff)
stm32/rcc: misc cleanups.
Diffstat (limited to 'examples/stm32h7/src/bin/fmc.rs')
-rw-r--r--examples/stm32h7/src/bin/fmc.rs6
1 files changed, 3 insertions, 3 deletions
diff --git a/examples/stm32h7/src/bin/fmc.rs b/examples/stm32h7/src/bin/fmc.rs
index cffd47093..54e2c3629 100644
--- a/examples/stm32h7/src/bin/fmc.rs
+++ b/examples/stm32h7/src/bin/fmc.rs
@@ -14,17 +14,17 @@ async fn main(_spawner: Spawner) {
14 let mut config = Config::default(); 14 let mut config = Config::default();
15 { 15 {
16 use embassy_stm32::rcc::*; 16 use embassy_stm32::rcc::*;
17 config.rcc.hsi = Some(Hsi::Mhz64); 17 config.rcc.hsi = Some(HSIPrescaler::DIV1);
18 config.rcc.csi = true; 18 config.rcc.csi = true;
19 config.rcc.pll_src = PllSource::Hsi;
20 config.rcc.pll1 = Some(Pll { 19 config.rcc.pll1 = Some(Pll {
20 source: PllSource::HSI,
21 prediv: PllPreDiv::DIV4, 21 prediv: PllPreDiv::DIV4,
22 mul: PllMul::MUL50, 22 mul: PllMul::MUL50,
23 divp: Some(PllDiv::DIV2), 23 divp: Some(PllDiv::DIV2),
24 divq: Some(PllDiv::DIV8), // 100mhz 24 divq: Some(PllDiv::DIV8), // 100mhz
25 divr: None, 25 divr: None,
26 }); 26 });
27 config.rcc.sys = Sysclk::Pll1P; // 400 Mhz 27 config.rcc.sys = Sysclk::PLL1_P; // 400 Mhz
28 config.rcc.ahb_pre = AHBPrescaler::DIV2; // 200 Mhz 28 config.rcc.ahb_pre = AHBPrescaler::DIV2; // 200 Mhz
29 config.rcc.apb1_pre = APBPrescaler::DIV2; // 100 Mhz 29 config.rcc.apb1_pre = APBPrescaler::DIV2; // 100 Mhz
30 config.rcc.apb2_pre = APBPrescaler::DIV2; // 100 Mhz 30 config.rcc.apb2_pre = APBPrescaler::DIV2; // 100 Mhz