diff options
| author | Dario Nieuwenhuis <[email protected]> | 2023-11-05 23:35:01 +0100 |
|---|---|---|
| committer | Dario Nieuwenhuis <[email protected]> | 2023-11-05 23:52:54 +0100 |
| commit | 0272deb158c4cc821e8f587283817a0fe5f82cf8 (patch) | |
| tree | 9774d81020c3da632e676017d471b1d2d06aae2e /examples/stm32h7/src/bin/low_level_timer_api.rs | |
| parent | c4a8b79dbc927e46fcc71879673ad3410aa3174b (diff) | |
stm32/rcc: add shared code for hsi48 with crs support.
Diffstat (limited to 'examples/stm32h7/src/bin/low_level_timer_api.rs')
| -rw-r--r-- | examples/stm32h7/src/bin/low_level_timer_api.rs | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/examples/stm32h7/src/bin/low_level_timer_api.rs b/examples/stm32h7/src/bin/low_level_timer_api.rs index e4bac8a5a..e0be495d1 100644 --- a/examples/stm32h7/src/bin/low_level_timer_api.rs +++ b/examples/stm32h7/src/bin/low_level_timer_api.rs | |||
| @@ -19,7 +19,6 @@ async fn main(_spawner: Spawner) { | |||
| 19 | use embassy_stm32::rcc::*; | 19 | use embassy_stm32::rcc::*; |
| 20 | config.rcc.hsi = Some(HSIPrescaler::DIV1); | 20 | config.rcc.hsi = Some(HSIPrescaler::DIV1); |
| 21 | config.rcc.csi = true; | 21 | config.rcc.csi = true; |
| 22 | config.rcc.hsi48 = true; // needed for RNG | ||
| 23 | config.rcc.pll1 = Some(Pll { | 22 | config.rcc.pll1 = Some(Pll { |
| 24 | source: PllSource::HSI, | 23 | source: PllSource::HSI, |
| 25 | prediv: PllPreDiv::DIV4, | 24 | prediv: PllPreDiv::DIV4, |