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authorelagil <[email protected]>2024-11-16 15:02:32 +0100
committerelagil <[email protected]>2024-11-16 15:02:32 +0100
commitd592875ca6d4df2b126e67603d32ed7f3e71910b (patch)
tree04a86d83160817fa4f06f63a5cdb85886f320636 /examples/stm32h7/src/bin/sai.rs
parent6c4b3d82b637fce5ab6efdc312d7852381d8ddeb (diff)
fix(SAI): disallow start without initial write
Diffstat (limited to 'examples/stm32h7/src/bin/sai.rs')
-rw-r--r--examples/stm32h7/src/bin/sai.rs1
1 files changed, 0 insertions, 1 deletions
diff --git a/examples/stm32h7/src/bin/sai.rs b/examples/stm32h7/src/bin/sai.rs
index 04d14bd6b..0594c838a 100644
--- a/examples/stm32h7/src/bin/sai.rs
+++ b/examples/stm32h7/src/bin/sai.rs
@@ -108,7 +108,6 @@ async fn main(_spawner: Spawner) {
108 let mut sai_receiver = Sai::new_synchronous(sub_block_rx, p.PE3, p.DMA1_CH1, rx_buffer, rx_config); 108 let mut sai_receiver = Sai::new_synchronous(sub_block_rx, p.PE3, p.DMA1_CH1, rx_buffer, rx_config);
109 109
110 sai_receiver.start(); 110 sai_receiver.start();
111 sai_transmitter.start();
112 111
113 let mut buf = [0u32; HALF_DMA_BUFFER_LENGTH]; 112 let mut buf = [0u32; HALF_DMA_BUFFER_LENGTH];
114 113