diff options
| author | Dario Nieuwenhuis <[email protected]> | 2023-10-23 01:48:09 +0200 |
|---|---|---|
| committer | Dario Nieuwenhuis <[email protected]> | 2023-10-23 17:36:21 +0200 |
| commit | a39ae12edcf23935df82d547fb2d997ca6b7c8d5 (patch) | |
| tree | d13df6dec747ab5d3af23c7dac1b12c085b26cfd /examples/stm32h7/src/bin/sdmmc.rs | |
| parent | 0ef1cb29f70c71d3c85f5b8b4ad3c7ce60babba8 (diff) | |
stm32/rcc: misc cleanups.
Diffstat (limited to 'examples/stm32h7/src/bin/sdmmc.rs')
| -rw-r--r-- | examples/stm32h7/src/bin/sdmmc.rs | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/examples/stm32h7/src/bin/sdmmc.rs b/examples/stm32h7/src/bin/sdmmc.rs index ecb8d6542..be968ff77 100644 --- a/examples/stm32h7/src/bin/sdmmc.rs +++ b/examples/stm32h7/src/bin/sdmmc.rs | |||
| @@ -18,17 +18,17 @@ async fn main(_spawner: Spawner) -> ! { | |||
| 18 | let mut config = Config::default(); | 18 | let mut config = Config::default(); |
| 19 | { | 19 | { |
| 20 | use embassy_stm32::rcc::*; | 20 | use embassy_stm32::rcc::*; |
| 21 | config.rcc.hsi = Some(Hsi::Mhz64); | 21 | config.rcc.hsi = Some(HSIPrescaler::DIV1); |
| 22 | config.rcc.csi = true; | 22 | config.rcc.csi = true; |
| 23 | config.rcc.pll_src = PllSource::Hsi; | ||
| 24 | config.rcc.pll1 = Some(Pll { | 23 | config.rcc.pll1 = Some(Pll { |
| 24 | source: PllSource::HSI, | ||
| 25 | prediv: PllPreDiv::DIV4, | 25 | prediv: PllPreDiv::DIV4, |
| 26 | mul: PllMul::MUL50, | 26 | mul: PllMul::MUL50, |
| 27 | divp: Some(PllDiv::DIV2), | 27 | divp: Some(PllDiv::DIV2), |
| 28 | divq: Some(PllDiv::DIV4), // default clock chosen by SDMMCSEL. 200 Mhz | 28 | divq: Some(PllDiv::DIV4), // default clock chosen by SDMMCSEL. 200 Mhz |
| 29 | divr: None, | 29 | divr: None, |
| 30 | }); | 30 | }); |
| 31 | config.rcc.sys = Sysclk::Pll1P; // 400 Mhz | 31 | config.rcc.sys = Sysclk::PLL1_P; // 400 Mhz |
| 32 | config.rcc.ahb_pre = AHBPrescaler::DIV2; // 200 Mhz | 32 | config.rcc.ahb_pre = AHBPrescaler::DIV2; // 200 Mhz |
| 33 | config.rcc.apb1_pre = APBPrescaler::DIV2; // 100 Mhz | 33 | config.rcc.apb1_pre = APBPrescaler::DIV2; // 100 Mhz |
| 34 | config.rcc.apb2_pre = APBPrescaler::DIV2; // 100 Mhz | 34 | config.rcc.apb2_pre = APBPrescaler::DIV2; // 100 Mhz |
