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authorDario Nieuwenhuis <[email protected]>2023-10-23 01:48:09 +0200
committerDario Nieuwenhuis <[email protected]>2023-10-23 17:36:21 +0200
commita39ae12edcf23935df82d547fb2d997ca6b7c8d5 (patch)
treed13df6dec747ab5d3af23c7dac1b12c085b26cfd /examples/stm32h7/src/bin/spi.rs
parent0ef1cb29f70c71d3c85f5b8b4ad3c7ce60babba8 (diff)
stm32/rcc: misc cleanups.
Diffstat (limited to 'examples/stm32h7/src/bin/spi.rs')
-rw-r--r--examples/stm32h7/src/bin/spi.rs6
1 files changed, 3 insertions, 3 deletions
diff --git a/examples/stm32h7/src/bin/spi.rs b/examples/stm32h7/src/bin/spi.rs
index f128d4a56..a8db0ff77 100644
--- a/examples/stm32h7/src/bin/spi.rs
+++ b/examples/stm32h7/src/bin/spi.rs
@@ -40,17 +40,17 @@ fn main() -> ! {
40 let mut config = Config::default(); 40 let mut config = Config::default();
41 { 41 {
42 use embassy_stm32::rcc::*; 42 use embassy_stm32::rcc::*;
43 config.rcc.hsi = Some(Hsi::Mhz64); 43 config.rcc.hsi = Some(HSIPrescaler::DIV1);
44 config.rcc.csi = true; 44 config.rcc.csi = true;
45 config.rcc.pll_src = PllSource::Hsi;
46 config.rcc.pll1 = Some(Pll { 45 config.rcc.pll1 = Some(Pll {
46 source: PllSource::HSI,
47 prediv: PllPreDiv::DIV4, 47 prediv: PllPreDiv::DIV4,
48 mul: PllMul::MUL50, 48 mul: PllMul::MUL50,
49 divp: Some(PllDiv::DIV2), 49 divp: Some(PllDiv::DIV2),
50 divq: Some(PllDiv::DIV8), // used by SPI3. 100Mhz. 50 divq: Some(PllDiv::DIV8), // used by SPI3. 100Mhz.
51 divr: None, 51 divr: None,
52 }); 52 });
53 config.rcc.sys = Sysclk::Pll1P; // 400 Mhz 53 config.rcc.sys = Sysclk::PLL1_P; // 400 Mhz
54 config.rcc.ahb_pre = AHBPrescaler::DIV2; // 200 Mhz 54 config.rcc.ahb_pre = AHBPrescaler::DIV2; // 200 Mhz
55 config.rcc.apb1_pre = APBPrescaler::DIV2; // 100 Mhz 55 config.rcc.apb1_pre = APBPrescaler::DIV2; // 100 Mhz
56 config.rcc.apb2_pre = APBPrescaler::DIV2; // 100 Mhz 56 config.rcc.apb2_pre = APBPrescaler::DIV2; // 100 Mhz