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authorAlejandroFNadal <[email protected]>2024-03-20 14:11:04 +0100
committerAlejandroFNadal <[email protected]>2024-03-20 14:11:04 +0100
commit2587ade63e30fc8aa222b4190515ab2e3fe51637 (patch)
treecada8ec03b17e82887cdb00b401b52a40d18a2a5 /examples/stm32h7/src
parent47ebec82b86a9dc9aa029ee7404b270cb0e70344 (diff)
Rust formatting for comments.
Diffstat (limited to 'examples/stm32h7/src')
-rw-r--r--examples/stm32h7/src/bin/eth.rs18
1 files changed, 9 insertions, 9 deletions
diff --git a/examples/stm32h7/src/bin/eth.rs b/examples/stm32h7/src/bin/eth.rs
index 825c16c6c..7c7964ecd 100644
--- a/examples/stm32h7/src/bin/eth.rs
+++ b/examples/stm32h7/src/bin/eth.rs
@@ -70,15 +70,15 @@ async fn main(spawner: Spawner) -> ! {
70 PACKETS.init(PacketQueue::<4, 4>::new()), 70 PACKETS.init(PacketQueue::<4, 4>::new()),
71 p.ETH, 71 p.ETH,
72 Irqs, 72 Irqs,
73 p.PA1, // ref_clk 73 p.PA1, // ref_clk
74 p.PA2, // mdio 74 p.PA2, // mdio
75 p.PC1, // eth_mdc 75 p.PC1, // eth_mdc
76 p.PA7, // CRS_DV: Carrier Sense 76 p.PA7, // CRS_DV: Carrier Sense
77 p.PC4, // RX_D0: Received Bit 0 77 p.PC4, // RX_D0: Received Bit 0
78 p.PC5, // RX_D1: Received Bit 1 78 p.PC5, // RX_D1: Received Bit 1
79 p.PG13,// TX_D0: Transmit Bit 0 79 p.PG13, // TX_D0: Transmit Bit 0
80 p.PB13,// TX_D1: Transmit Bit 1 80 p.PB13, // TX_D1: Transmit Bit 1
81 p.PG11,// TX_EN: Transmit Enable 81 p.PG11, // TX_EN: Transmit Enable
82 GenericSMI::new(0), 82 GenericSMI::new(0),
83 mac_addr, 83 mac_addr,
84 ); 84 );