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authorbors[bot] <26634292+bors[bot]@users.noreply.github.com>2022-01-04 12:31:55 +0000
committerGitHub <[email protected]>2022-01-04 12:31:55 +0000
commitb2a85ee519067d3290e328f9ad047184ff033cd7 (patch)
tree70c550e647b2a1754b50b20cd365bcc67939986d /examples/stm32h7/src
parentf744b74e90d3bb1a571c10f0749f22132b51d303 (diff)
parent89b009b11d7c45533f53a41c6586ba514cf7be58 (diff)
Merge #565
565: stm32: RCC cleanups r=Dirbaio a=Dirbaio Co-authored-by: Dario Nieuwenhuis <[email protected]>
Diffstat (limited to 'examples/stm32h7/src')
-rw-r--r--examples/stm32h7/src/bin/camera.rs2
-rw-r--r--examples/stm32h7/src/example_common.rs1
2 files changed, 0 insertions, 3 deletions
diff --git a/examples/stm32h7/src/bin/camera.rs b/examples/stm32h7/src/bin/camera.rs
index 2fa742b83..d94592071 100644
--- a/examples/stm32h7/src/bin/camera.rs
+++ b/examples/stm32h7/src/bin/camera.rs
@@ -34,8 +34,6 @@ pub fn config() -> Config {
34 config.rcc.sys_ck = Some(400.mhz().into()); 34 config.rcc.sys_ck = Some(400.mhz().into());
35 config.rcc.hclk = Some(400.mhz().into()); 35 config.rcc.hclk = Some(400.mhz().into());
36 config.rcc.pll1.q_ck = Some(100.mhz().into()); 36 config.rcc.pll1.q_ck = Some(100.mhz().into());
37 config.rcc.enable_dma1 = true;
38 config.rcc.enable_dma2 = true;
39 config.rcc.pclk1 = Some(100.mhz().into()); 37 config.rcc.pclk1 = Some(100.mhz().into());
40 config.rcc.pclk2 = Some(100.mhz().into()); 38 config.rcc.pclk2 = Some(100.mhz().into());
41 config.rcc.pclk3 = Some(100.mhz().into()); 39 config.rcc.pclk3 = Some(100.mhz().into());
diff --git a/examples/stm32h7/src/example_common.rs b/examples/stm32h7/src/example_common.rs
index 2e26730fa..524bee6d9 100644
--- a/examples/stm32h7/src/example_common.rs
+++ b/examples/stm32h7/src/example_common.rs
@@ -23,6 +23,5 @@ pub fn config() -> Config {
23 let mut config = Config::default(); 23 let mut config = Config::default();
24 config.rcc.sys_ck = Some(400.mhz().into()); 24 config.rcc.sys_ck = Some(400.mhz().into());
25 config.rcc.pll1.q_ck = Some(100.mhz().into()); 25 config.rcc.pll1.q_ck = Some(100.mhz().into());
26 config.rcc.enable_dma1 = true;
27 config 26 config
28} 27}