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authorragarnoy <[email protected]>2025-05-10 02:22:48 +0200
committerragarnoy <[email protected]>2025-05-10 02:22:48 +0200
commitcf60b110668f1650836f7d81bf41b629603ae6d6 (patch)
treec1e8d6efeb65a070d9a0639bbb098f5d49a4daf0 /examples/stm32h755cm7/src/bin/intercore.rs
parent90404a8e524a0d06ce35230dea7ff4d3e4d0375a (diff)
rustfmt
Diffstat (limited to 'examples/stm32h755cm7/src/bin/intercore.rs')
-rw-r--r--examples/stm32h755cm7/src/bin/intercore.rs17
1 files changed, 8 insertions, 9 deletions
diff --git a/examples/stm32h755cm7/src/bin/intercore.rs b/examples/stm32h755cm7/src/bin/intercore.rs
index 154b1682b..5783d05e1 100644
--- a/examples/stm32h755cm7/src/bin/intercore.rs
+++ b/examples/stm32h755cm7/src/bin/intercore.rs
@@ -75,7 +75,7 @@ mod shared {
75 value 75 value
76 } 76 }
77 } 77 }
78 78
79 #[link_section = ".ram_d3"] 79 #[link_section = ".ram_d3"]
80 pub static SHARED_LED_STATE: SharedLedState = SharedLedState::new(); 80 pub static SHARED_LED_STATE: SharedLedState = SharedLedState::new();
81 81
@@ -93,8 +93,8 @@ use embassy_time::Timer;
93use {defmt_rtt as _, panic_probe as _}; 93use {defmt_rtt as _, panic_probe as _};
94 94
95// Import cortex_m for MPU configuration 95// Import cortex_m for MPU configuration
96use cortex_m::peripheral::{MPU, SCB};
97use cortex_m::asm; 96use cortex_m::asm;
97use cortex_m::peripheral::{MPU, SCB};
98 98
99// Use our shared state from the module 99// Use our shared state from the module
100use shared::{SHARED_LED_STATE, SRAM4_BASE_ADDRESS, SRAM4_REGION_NUMBER, SRAM4_SIZE_LOG2}; 100use shared::{SHARED_LED_STATE, SRAM4_BASE_ADDRESS, SRAM4_REGION_NUMBER, SRAM4_SIZE_LOG2};
@@ -116,8 +116,7 @@ fn configure_mpu_non_cacheable(mpu: &mut MPU, _scb: &mut SCB) {
116 116
117 // Set base address (SRAM4 = 0x38000000) with VALID bit and region number 117 // Set base address (SRAM4 = 0x38000000) with VALID bit and region number
118 mpu.rbar.write( 118 mpu.rbar.write(
119 SRAM4_BASE_ADDRESS | 119 SRAM4_BASE_ADDRESS | (1 << 4), // Region number = 0 (explicit in RBAR)
120 (1 << 4) // Region number = 0 (explicit in RBAR)
121 ); 120 );
122 121
123 // Configure region attributes: 122 // Configure region attributes:
@@ -129,7 +128,7 @@ fn configure_mpu_non_cacheable(mpu: &mut MPU, _scb: &mut SCB) {
129 (1 << 0) | // ENABLE=1 128 (1 << 0) | // ENABLE=1
130 (3 << 24) | // AP=3 (Full access) 129 (3 << 24) | // AP=3 (Full access)
131 (1 << 19) | // TEX=1 130 (1 << 19) | // TEX=1
132 (1 << 18); // S=1 (Shareable) 131 (1 << 18); // S=1 (Shareable)
133 132
134 mpu.rasr.write(rasr_value); 133 mpu.rasr.write(rasr_value);
135 134
@@ -151,7 +150,7 @@ async fn main(spawner: Spawner) -> ! {
151 let mut cp = cortex_m::Peripherals::take().unwrap(); 150 let mut cp = cortex_m::Peripherals::take().unwrap();
152 let mpu = &mut cp.MPU; 151 let mpu = &mut cp.MPU;
153 let scb = &mut cp.SCB; 152 let scb = &mut cp.SCB;
154 153
155 // Configure MPU without disabling caches 154 // Configure MPU without disabling caches
156 configure_mpu_non_cacheable(mpu, scb); 155 configure_mpu_non_cacheable(mpu, scb);
157 } 156 }
@@ -190,9 +189,9 @@ async fn main(spawner: Spawner) -> ! {
190 info!("CM7: Magic value = 0x{:X}", magic); 189 info!("CM7: Magic value = 0x{:X}", magic);
191 190
192 // Initialize shared memory state 191 // Initialize shared memory state
193 SHARED_LED_STATE.set_led(true, false); // Green LED off 192 SHARED_LED_STATE.set_led(true, false); // Green LED off
194 SHARED_LED_STATE.set_led(false, false); // Yellow LED off 193 SHARED_LED_STATE.set_led(false, false); // Yellow LED off
195 194
196 // Main loop - update shared memory values 195 // Main loop - update shared memory values
197 let mut green_state = false; 196 let mut green_state = false;
198 let mut yellow_state = false; 197 let mut yellow_state = false;
@@ -223,4 +222,4 @@ async fn main(spawner: Spawner) -> ! {
223 // Wait 100ms before next cycle 222 // Wait 100ms before next cycle
224 Timer::after_millis(100).await; 223 Timer::after_millis(100).await;
225 } 224 }
226} \ No newline at end of file 225}