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| author | leftger <[email protected]> | 2025-07-27 09:38:38 -0700 |
|---|---|---|
| committer | GitHub <[email protected]> | 2025-07-27 09:38:38 -0700 |
| commit | b9e643d5c2d7192143e91db83b9e8377f0fbcacc (patch) | |
| tree | 86a695a05ccb70be67613ea742b14094a7aca362 /examples/stm32h7rs/src/bin/eth.rs | |
| parent | 1b3674b30ac2b7deb8e19b132d5ba15351cb8ebd (diff) | |
| parent | 77a8bc27e9c34e363f321132ebb9e8d8ff684a9f (diff) | |
Merge branch 'main' into feat/stm32wba-rcc-pll-support
Diffstat (limited to 'examples/stm32h7rs/src/bin/eth.rs')
| -rw-r--r-- | examples/stm32h7rs/src/bin/eth.rs | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/examples/stm32h7rs/src/bin/eth.rs b/examples/stm32h7rs/src/bin/eth.rs index 6d246bb09..d8002e9ba 100644 --- a/examples/stm32h7rs/src/bin/eth.rs +++ b/examples/stm32h7rs/src/bin/eth.rs | |||
| @@ -41,6 +41,8 @@ async fn main(spawner: Spawner) -> ! { | |||
| 41 | divp: Some(PllDiv::DIV2), | 41 | divp: Some(PllDiv::DIV2), |
| 42 | divq: None, | 42 | divq: None, |
| 43 | divr: None, | 43 | divr: None, |
| 44 | divs: None, | ||
| 45 | divt: None, | ||
| 44 | }); | 46 | }); |
| 45 | config.rcc.sys = Sysclk::PLL1_P; // 400 Mhz | 47 | config.rcc.sys = Sysclk::PLL1_P; // 400 Mhz |
| 46 | config.rcc.ahb_pre = AHBPrescaler::DIV2; // 200 Mhz | 48 | config.rcc.ahb_pre = AHBPrescaler::DIV2; // 200 Mhz |