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authorRukai <[email protected]>2021-07-03 22:05:12 +1000
committerDario Nieuwenhuis <[email protected]>2021-07-05 01:54:29 +0200
commit25d4b2ea2665bcf8907caf8b01d5223c615448c3 (patch)
tree53c7d2ec20855aa404363ccf81e488561beffda9 /examples/stm32l4/src/bin
parent8615ffb523edbfa10b9bc13c24668da760cf06c5 (diff)
fix stm32 warnings
Diffstat (limited to 'examples/stm32l4/src/bin')
-rw-r--r--examples/stm32l4/src/bin/adc.rs29
-rw-r--r--examples/stm32l4/src/bin/dac.rs16
2 files changed, 11 insertions, 34 deletions
diff --git a/examples/stm32l4/src/bin/adc.rs b/examples/stm32l4/src/bin/adc.rs
index fe97fb0b1..a909e1bb2 100644
--- a/examples/stm32l4/src/bin/adc.rs
+++ b/examples/stm32l4/src/bin/adc.rs
@@ -1,5 +1,6 @@
1#![no_std] 1#![no_std]
2#![no_main] 2#![no_main]
3#![allow(incomplete_features)]
3#![feature(trait_alias)] 4#![feature(trait_alias)]
4#![feature(min_type_alias_impl_trait)] 5#![feature(min_type_alias_impl_trait)]
5#![feature(impl_trait_in_bindings)] 6#![feature(impl_trait_in_bindings)]
@@ -8,23 +9,15 @@
8#[path = "../example_common.rs"] 9#[path = "../example_common.rs"]
9mod example_common; 10mod example_common;
10 11
11use embassy_stm32::gpio::{Input, Level, NoPin, Output, Pull};
12use embedded_hal::digital::v2::{InputPin, OutputPin};
13use example_common::*; 12use example_common::*;
14 13
15use cortex_m_rt::entry; 14use cortex_m_rt::entry;
16//use stm32f4::stm32f429 as pac; 15//use stm32f4::stm32f429 as pac;
17use cortex_m::delay::Delay; 16use cortex_m::delay::Delay;
18use embassy_stm32::adc::{Adc, Resolution}; 17use embassy_stm32::adc::{Adc, Resolution};
19use embassy_stm32::dac::{Channel, Dac, Value};
20use embassy_stm32::spi::{ByteOrder, Config, Spi, MODE_0};
21use embassy_stm32::time::Hertz;
22use embedded_hal::blocking::spi::Transfer;
23use micromath::F32Ext;
24use stm32l4::stm32l4x5 as pac; 18use stm32l4::stm32l4x5 as pac;
25use stm32l4xx_hal::gpio::PA4;
26use stm32l4xx_hal::rcc::PllSource; 19use stm32l4xx_hal::rcc::PllSource;
27use stm32l4xx_hal::{prelude::*, rcc}; 20use stm32l4xx_hal::prelude::*;
28 21
29#[entry] 22#[entry]
30fn main() -> ! { 23fn main() -> ! {
@@ -36,11 +29,11 @@ fn main() -> ! {
36 let mut rcc = pp.RCC.constrain(); 29 let mut rcc = pp.RCC.constrain();
37 let mut pwr = pp.PWR.constrain(&mut rcc.apb1r1); 30 let mut pwr = pp.PWR.constrain(&mut rcc.apb1r1);
38 31
39 let mut delay = Delay::new(cp.SYST, 80_000_000); 32 let delay = Delay::new(cp.SYST, 80_000_000);
40 33
41 // TRY the other clock configuration 34 // TRY the other clock configuration
42 // let clocks = rcc.cfgr.freeze(&mut flash.acr); 35 // let clocks = rcc.cfgr.freeze(&mut flash.acr);
43 let clocks = rcc 36 rcc
44 .cfgr 37 .cfgr
45 .sysclk(80.mhz()) 38 .sysclk(80.mhz())
46 .pclk1(80.mhz()) 39 .pclk1(80.mhz())
@@ -76,7 +69,7 @@ fn main() -> ! {
76 69
77 let p = embassy_stm32::init(Default::default()); 70 let p = embassy_stm32::init(Default::default());
78 71
79 let (mut adc, mut delay) = Adc::new(p.ADC1, delay); 72 let (mut adc, _) = Adc::new(p.ADC1, delay);
80 //adc.enable_vref(); 73 //adc.enable_vref();
81 adc.set_resolution(Resolution::EightBit); 74 adc.set_resolution(Resolution::EightBit);
82 let mut channel = p.PC0; 75 let mut channel = p.PC0;
@@ -86,15 +79,3 @@ fn main() -> ! {
86 info!("--> {}", v); 79 info!("--> {}", v);
87 } 80 }
88} 81}
89
90fn to_sine_wave(v: u8) -> u8 {
91 if v >= 128 {
92 // top half
93 let r = 3.14 * ((v - 128) as f32 / 128.0);
94 (r.sin() * 128.0 + 127.0) as u8
95 } else {
96 // bottom half
97 let r = 3.14 + 3.14 * (v as f32 / 128.0);
98 (r.sin() * 128.0 + 127.0) as u8
99 }
100}
diff --git a/examples/stm32l4/src/bin/dac.rs b/examples/stm32l4/src/bin/dac.rs
index 0ca40fbdb..5317ac35f 100644
--- a/examples/stm32l4/src/bin/dac.rs
+++ b/examples/stm32l4/src/bin/dac.rs
@@ -1,5 +1,6 @@
1#![no_std] 1#![no_std]
2#![no_main] 2#![no_main]
3#![allow(incomplete_features)]
3#![feature(trait_alias)] 4#![feature(trait_alias)]
4#![feature(min_type_alias_impl_trait)] 5#![feature(min_type_alias_impl_trait)]
5#![feature(impl_trait_in_bindings)] 6#![feature(impl_trait_in_bindings)]
@@ -8,20 +9,15 @@
8#[path = "../example_common.rs"] 9#[path = "../example_common.rs"]
9mod example_common; 10mod example_common;
10 11
11use embassy_stm32::gpio::{Input, Level, NoPin, Output, Pull}; 12use embassy_stm32::gpio::NoPin;
12use embedded_hal::digital::v2::{InputPin, OutputPin};
13use example_common::*; 13use example_common::*;
14 14
15use cortex_m_rt::entry; 15use cortex_m_rt::entry;
16//use stm32f4::stm32f429 as pac; 16//use stm32f4::stm32f429 as pac;
17use embassy_stm32::dac::{Channel, Dac, Value}; 17use embassy_stm32::dac::{Channel, Dac, Value};
18use embassy_stm32::spi::{ByteOrder, Config, Spi, MODE_0};
19use embassy_stm32::time::Hertz;
20use embedded_hal::blocking::spi::Transfer;
21use stm32l4::stm32l4x5 as pac; 18use stm32l4::stm32l4x5 as pac;
22use stm32l4xx_hal::gpio::PA4;
23use stm32l4xx_hal::rcc::PllSource; 19use stm32l4xx_hal::rcc::PllSource;
24use stm32l4xx_hal::{prelude::*, rcc}; 20use stm32l4xx_hal::{prelude::*};
25 21
26#[entry] 22#[entry]
27fn main() -> ! { 23fn main() -> ! {
@@ -34,7 +30,7 @@ fn main() -> ! {
34 30
35 // TRY the other clock configuration 31 // TRY the other clock configuration
36 // let clocks = rcc.cfgr.freeze(&mut flash.acr); 32 // let clocks = rcc.cfgr.freeze(&mut flash.acr);
37 let clocks = rcc 33 rcc
38 .cfgr 34 .cfgr
39 .sysclk(80.mhz()) 35 .sysclk(80.mhz())
40 .pclk1(80.mhz()) 36 .pclk1(80.mhz())
@@ -71,8 +67,8 @@ fn main() -> ! {
71 67
72 loop { 68 loop {
73 for v in 0..=255 { 69 for v in 0..=255 {
74 dac.set(Channel::Ch1, Value::Bit8(to_sine_wave(v))); 70 unwrap!(dac.set(Channel::Ch1, Value::Bit8(to_sine_wave(v))));
75 dac.trigger(Channel::Ch1); 71 unwrap!(dac.trigger(Channel::Ch1));
76 } 72 }
77 } 73 }
78} 74}