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authorDario Nieuwenhuis <[email protected]>2023-11-13 00:52:01 +0100
committerDario Nieuwenhuis <[email protected]>2023-11-13 00:52:01 +0100
commit4fe344ebc0f4e030ff7a03755f27e66e9ad0476f (patch)
treef4c40f8f346d52f2180ccf39f2d811337a2e9621 /examples/stm32l4/src
parent39c737162185adb4f30f18f700da08a55be6b55a (diff)
stm32/rcc: consistent casing and naming for PLL enums.
Diffstat (limited to 'examples/stm32l4/src')
-rw-r--r--examples/stm32l4/src/bin/rng.rs4
-rw-r--r--examples/stm32l4/src/bin/rtc.rs2
-rw-r--r--examples/stm32l4/src/bin/spe_adin1110_http_server.rs4
-rw-r--r--examples/stm32l4/src/bin/usb_serial.rs2
4 files changed, 6 insertions, 6 deletions
diff --git a/examples/stm32l4/src/bin/rng.rs b/examples/stm32l4/src/bin/rng.rs
index 553d11c03..e5ad56fb9 100644
--- a/examples/stm32l4/src/bin/rng.rs
+++ b/examples/stm32l4/src/bin/rng.rs
@@ -4,7 +4,7 @@
4 4
5use defmt::*; 5use defmt::*;
6use embassy_executor::Spawner; 6use embassy_executor::Spawner;
7use embassy_stm32::rcc::{ClockSrc, PLLSource, Pll, PllMul, PllPreDiv, PllQDiv, PllRDiv}; 7use embassy_stm32::rcc::{ClockSrc, Pll, PllMul, PllPreDiv, PllQDiv, PllRDiv, PllSource};
8use embassy_stm32::rng::Rng; 8use embassy_stm32::rng::Rng;
9use embassy_stm32::{bind_interrupts, peripherals, rng, Config}; 9use embassy_stm32::{bind_interrupts, peripherals, rng, Config};
10use {defmt_rtt as _, panic_probe as _}; 10use {defmt_rtt as _, panic_probe as _};
@@ -19,7 +19,7 @@ async fn main(_spawner: Spawner) {
19 config.rcc.mux = ClockSrc::PLL1_R; 19 config.rcc.mux = ClockSrc::PLL1_R;
20 config.rcc.hsi = true; 20 config.rcc.hsi = true;
21 config.rcc.pll = Some(Pll { 21 config.rcc.pll = Some(Pll {
22 source: PLLSource::HSI, 22 source: PllSource::HSI,
23 prediv: PllPreDiv::DIV1, 23 prediv: PllPreDiv::DIV1,
24 mul: PllMul::MUL18, 24 mul: PllMul::MUL18,
25 divp: None, 25 divp: None,
diff --git a/examples/stm32l4/src/bin/rtc.rs b/examples/stm32l4/src/bin/rtc.rs
index 69527c9ad..d2a2aa1f2 100644
--- a/examples/stm32l4/src/bin/rtc.rs
+++ b/examples/stm32l4/src/bin/rtc.rs
@@ -22,7 +22,7 @@ async fn main(_spawner: Spawner) {
22 mode: HseMode::Oscillator, 22 mode: HseMode::Oscillator,
23 }); 23 });
24 config.rcc.pll = Some(Pll { 24 config.rcc.pll = Some(Pll {
25 source: PLLSource::HSE, 25 source: PllSource::HSE,
26 prediv: PllPreDiv::DIV1, 26 prediv: PllPreDiv::DIV1,
27 mul: PllMul::MUL20, 27 mul: PllMul::MUL20,
28 divp: None, 28 divp: None,
diff --git a/examples/stm32l4/src/bin/spe_adin1110_http_server.rs b/examples/stm32l4/src/bin/spe_adin1110_http_server.rs
index 62caeea55..3a7e5370c 100644
--- a/examples/stm32l4/src/bin/spe_adin1110_http_server.rs
+++ b/examples/stm32l4/src/bin/spe_adin1110_http_server.rs
@@ -75,7 +75,7 @@ async fn main(spawner: Spawner) {
75 let mut config = embassy_stm32::Config::default(); 75 let mut config = embassy_stm32::Config::default();
76 { 76 {
77 use embassy_stm32::rcc::*; 77 use embassy_stm32::rcc::*;
78 // 80Mhz clock (Source: 8 / SrcDiv: 1 * PLLMul 20 / ClkDiv 2) 78 // 80Mhz clock (Source: 8 / SrcDiv: 1 * PllMul 20 / ClkDiv 2)
79 // 80MHz highest frequency for flash 0 wait. 79 // 80MHz highest frequency for flash 0 wait.
80 config.rcc.mux = ClockSrc::PLL1_R; 80 config.rcc.mux = ClockSrc::PLL1_R;
81 config.rcc.hse = Some(Hse { 81 config.rcc.hse = Some(Hse {
@@ -83,7 +83,7 @@ async fn main(spawner: Spawner) {
83 mode: HseMode::Oscillator, 83 mode: HseMode::Oscillator,
84 }); 84 });
85 config.rcc.pll = Some(Pll { 85 config.rcc.pll = Some(Pll {
86 source: PLLSource::HSE, 86 source: PllSource::HSE,
87 prediv: PllPreDiv::DIV1, 87 prediv: PllPreDiv::DIV1,
88 mul: PllMul::MUL20, 88 mul: PllMul::MUL20,
89 divp: None, 89 divp: None,
diff --git a/examples/stm32l4/src/bin/usb_serial.rs b/examples/stm32l4/src/bin/usb_serial.rs
index d977398f5..4baf5f05d 100644
--- a/examples/stm32l4/src/bin/usb_serial.rs
+++ b/examples/stm32l4/src/bin/usb_serial.rs
@@ -27,7 +27,7 @@ async fn main(_spawner: Spawner) {
27 config.rcc.mux = ClockSrc::PLL1_R; 27 config.rcc.mux = ClockSrc::PLL1_R;
28 config.rcc.hsi = true; 28 config.rcc.hsi = true;
29 config.rcc.pll = Some(Pll { 29 config.rcc.pll = Some(Pll {
30 source: PLLSource::HSI, 30 source: PllSource::HSI,
31 prediv: PllPreDiv::DIV1, 31 prediv: PllPreDiv::DIV1,
32 mul: PllMul::MUL10, 32 mul: PllMul::MUL10,
33 divp: None, 33 divp: None,