diff options
| author | eZio Pan <[email protected]> | 2023-12-25 21:29:17 +0800 |
|---|---|---|
| committer | eZio Pan <[email protected]> | 2023-12-25 22:03:32 +0800 |
| commit | d90a97aa4c5977e3d071fb4ed94656e6666d965c (patch) | |
| tree | 04a904e569fb1870817aff3335958ef4e20b56e7 /examples/stm32l4/src | |
| parent | 8b6c6c7df68088abc4a572a825a03e79c9b8694a (diff) | |
update metapac after stm32-data PR323
and refactor a few code with cargo clippy
Diffstat (limited to 'examples/stm32l4/src')
| -rw-r--r-- | examples/stm32l4/src/bin/dac_dma.rs | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/examples/stm32l4/src/bin/dac_dma.rs b/examples/stm32l4/src/bin/dac_dma.rs index 64c541caa..8e5098557 100644 --- a/examples/stm32l4/src/bin/dac_dma.rs +++ b/examples/stm32l4/src/bin/dac_dma.rs | |||
| @@ -4,7 +4,7 @@ | |||
| 4 | use defmt::*; | 4 | use defmt::*; |
| 5 | use embassy_executor::Spawner; | 5 | use embassy_executor::Spawner; |
| 6 | use embassy_stm32::dac::{DacCh1, DacCh2, ValueArray}; | 6 | use embassy_stm32::dac::{DacCh1, DacCh2, ValueArray}; |
| 7 | use embassy_stm32::pac::timer::vals::{Mms, Opm}; | 7 | use embassy_stm32::pac::timer::vals::Mms; |
| 8 | use embassy_stm32::peripherals::{DAC1, DMA1_CH3, DMA1_CH4, TIM6, TIM7}; | 8 | use embassy_stm32::peripherals::{DAC1, DMA1_CH3, DMA1_CH4, TIM6, TIM7}; |
| 9 | use embassy_stm32::rcc::low_level::RccPeripheral; | 9 | use embassy_stm32::rcc::low_level::RccPeripheral; |
| 10 | use embassy_stm32::time::Hertz; | 10 | use embassy_stm32::time::Hertz; |
| @@ -49,7 +49,7 @@ async fn dac_task1(mut dac: DacCh1<'static, DAC1, DMA1_CH3>) { | |||
| 49 | TIM6::regs().arr().modify(|w| w.set_arr(reload as u16 - 1)); | 49 | TIM6::regs().arr().modify(|w| w.set_arr(reload as u16 - 1)); |
| 50 | TIM6::regs().cr2().modify(|w| w.set_mms(Mms::UPDATE)); | 50 | TIM6::regs().cr2().modify(|w| w.set_mms(Mms::UPDATE)); |
| 51 | TIM6::regs().cr1().modify(|w| { | 51 | TIM6::regs().cr1().modify(|w| { |
| 52 | w.set_opm(Opm::DISABLED); | 52 | w.set_opm(false); |
| 53 | w.set_cen(true); | 53 | w.set_cen(true); |
| 54 | }); | 54 | }); |
| 55 | 55 | ||
| @@ -86,7 +86,7 @@ async fn dac_task2(mut dac: DacCh2<'static, DAC1, DMA1_CH4>) { | |||
| 86 | TIM7::regs().arr().modify(|w| w.set_arr(reload as u16 - 1)); | 86 | TIM7::regs().arr().modify(|w| w.set_arr(reload as u16 - 1)); |
| 87 | TIM7::regs().cr2().modify(|w| w.set_mms(Mms::UPDATE)); | 87 | TIM7::regs().cr2().modify(|w| w.set_mms(Mms::UPDATE)); |
| 88 | TIM7::regs().cr1().modify(|w| { | 88 | TIM7::regs().cr1().modify(|w| { |
| 89 | w.set_opm(Opm::DISABLED); | 89 | w.set_opm(false); |
| 90 | w.set_cen(true); | 90 | w.set_cen(true); |
| 91 | }); | 91 | }); |
| 92 | 92 | ||
