diff options
| author | Dario Nieuwenhuis <[email protected]> | 2021-07-05 03:09:42 +0200 |
|---|---|---|
| committer | Dario Nieuwenhuis <[email protected]> | 2021-07-05 03:18:23 +0200 |
| commit | ecc151d4e28394ed2dcec466e86ea1880095f9aa (patch) | |
| tree | 76ec36764d49225112056f8e3ef38d40ad5f7cde /examples/stm32l4 | |
| parent | 7ebd4e3aa946a4b5aeea086959a38c94487470a3 (diff) | |
stm32/adc: simplify delay handling
Diffstat (limited to 'examples/stm32l4')
| -rw-r--r-- | examples/stm32l4/src/bin/adc.rs | 9 |
1 files changed, 4 insertions, 5 deletions
diff --git a/examples/stm32l4/src/bin/adc.rs b/examples/stm32l4/src/bin/adc.rs index a909e1bb2..a3c44d3c1 100644 --- a/examples/stm32l4/src/bin/adc.rs +++ b/examples/stm32l4/src/bin/adc.rs | |||
| @@ -16,8 +16,8 @@ use cortex_m_rt::entry; | |||
| 16 | use cortex_m::delay::Delay; | 16 | use cortex_m::delay::Delay; |
| 17 | use embassy_stm32::adc::{Adc, Resolution}; | 17 | use embassy_stm32::adc::{Adc, Resolution}; |
| 18 | use stm32l4::stm32l4x5 as pac; | 18 | use stm32l4::stm32l4x5 as pac; |
| 19 | use stm32l4xx_hal::rcc::PllSource; | ||
| 20 | use stm32l4xx_hal::prelude::*; | 19 | use stm32l4xx_hal::prelude::*; |
| 20 | use stm32l4xx_hal::rcc::PllSource; | ||
| 21 | 21 | ||
| 22 | #[entry] | 22 | #[entry] |
| 23 | fn main() -> ! { | 23 | fn main() -> ! { |
| @@ -29,12 +29,11 @@ fn main() -> ! { | |||
| 29 | let mut rcc = pp.RCC.constrain(); | 29 | let mut rcc = pp.RCC.constrain(); |
| 30 | let mut pwr = pp.PWR.constrain(&mut rcc.apb1r1); | 30 | let mut pwr = pp.PWR.constrain(&mut rcc.apb1r1); |
| 31 | 31 | ||
| 32 | let delay = Delay::new(cp.SYST, 80_000_000); | 32 | let mut delay = Delay::new(cp.SYST, 80_000_000); |
| 33 | 33 | ||
| 34 | // TRY the other clock configuration | 34 | // TRY the other clock configuration |
| 35 | // let clocks = rcc.cfgr.freeze(&mut flash.acr); | 35 | // let clocks = rcc.cfgr.freeze(&mut flash.acr); |
| 36 | rcc | 36 | rcc.cfgr |
| 37 | .cfgr | ||
| 38 | .sysclk(80.mhz()) | 37 | .sysclk(80.mhz()) |
| 39 | .pclk1(80.mhz()) | 38 | .pclk1(80.mhz()) |
| 40 | .pclk2(80.mhz()) | 39 | .pclk2(80.mhz()) |
| @@ -69,7 +68,7 @@ fn main() -> ! { | |||
| 69 | 68 | ||
| 70 | let p = embassy_stm32::init(Default::default()); | 69 | let p = embassy_stm32::init(Default::default()); |
| 71 | 70 | ||
| 72 | let (mut adc, _) = Adc::new(p.ADC1, delay); | 71 | let mut adc = Adc::new(p.ADC1, &mut delay); |
| 73 | //adc.enable_vref(); | 72 | //adc.enable_vref(); |
| 74 | adc.set_resolution(Resolution::EightBit); | 73 | adc.set_resolution(Resolution::EightBit); |
| 75 | let mut channel = p.PC0; | 74 | let mut channel = p.PC0; |
