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authorpbert <[email protected]>2023-10-11 21:38:41 +0200
committerpbert <[email protected]>2023-10-12 11:04:44 +0200
commitecdd7c0e2f9dcc07e53e136557140d3ccc6a5ee1 (patch)
tree6db9bf875d3e83d94f6bf8e8a2e7ff03a83c5bb4 /examples/stm32l4
parentd7d79f3068a4a2d883b078b8900ad194f7c98203 (diff)
enable clock first
Diffstat (limited to 'examples/stm32l4')
-rw-r--r--examples/stm32l4/src/bin/dac_dma.rs4
1 files changed, 2 insertions, 2 deletions
diff --git a/examples/stm32l4/src/bin/dac_dma.rs b/examples/stm32l4/src/bin/dac_dma.rs
index 83d48f221..98f37f906 100644
--- a/examples/stm32l4/src/bin/dac_dma.rs
+++ b/examples/stm32l4/src/bin/dac_dma.rs
@@ -51,7 +51,7 @@ async fn dac_task1(mut dac: Dac1Type) {
51 dac.select_trigger(embassy_stm32::dac::Ch1Trigger::Tim6).unwrap(); 51 dac.select_trigger(embassy_stm32::dac::Ch1Trigger::Tim6).unwrap();
52 dac.enable_channel().unwrap(); 52 dac.enable_channel().unwrap();
53 53
54 TIM6::reset_and_enable(); 54 TIM6::enable_and_reset();
55 TIM6::regs().arr().modify(|w| w.set_arr(reload as u16 - 1)); 55 TIM6::regs().arr().modify(|w| w.set_arr(reload as u16 - 1));
56 TIM6::regs().cr2().modify(|w| w.set_mms(Mms::UPDATE)); 56 TIM6::regs().cr2().modify(|w| w.set_mms(Mms::UPDATE));
57 TIM6::regs().cr1().modify(|w| { 57 TIM6::regs().cr1().modify(|w| {
@@ -90,7 +90,7 @@ async fn dac_task2(mut dac: Dac2Type) {
90 error!("Reload value {} below threshold!", reload); 90 error!("Reload value {} below threshold!", reload);
91 } 91 }
92 92
93 TIM7::reset_and_enable(); 93 TIM7::enable_and_reset();
94 TIM7::regs().arr().modify(|w| w.set_arr(reload as u16 - 1)); 94 TIM7::regs().arr().modify(|w| w.set_arr(reload as u16 - 1));
95 TIM7::regs().cr2().modify(|w| w.set_mms(Mms::UPDATE)); 95 TIM7::regs().cr2().modify(|w| w.set_mms(Mms::UPDATE));
96 TIM7::regs().cr1().modify(|w| { 96 TIM7::regs().cr1().modify(|w| {