diff options
| author | Dario Nieuwenhuis <[email protected]> | 2023-11-13 00:52:01 +0100 |
|---|---|---|
| committer | Dario Nieuwenhuis <[email protected]> | 2023-11-13 00:52:01 +0100 |
| commit | 4fe344ebc0f4e030ff7a03755f27e66e9ad0476f (patch) | |
| tree | f4c40f8f346d52f2180ccf39f2d811337a2e9621 /examples/stm32l5/src/bin/usb_ethernet.rs | |
| parent | 39c737162185adb4f30f18f700da08a55be6b55a (diff) | |
stm32/rcc: consistent casing and naming for PLL enums.
Diffstat (limited to 'examples/stm32l5/src/bin/usb_ethernet.rs')
| -rw-r--r-- | examples/stm32l5/src/bin/usb_ethernet.rs | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/examples/stm32l5/src/bin/usb_ethernet.rs b/examples/stm32l5/src/bin/usb_ethernet.rs index 923193abf..0b0a0e2db 100644 --- a/examples/stm32l5/src/bin/usb_ethernet.rs +++ b/examples/stm32l5/src/bin/usb_ethernet.rs | |||
| @@ -49,7 +49,7 @@ async fn main(spawner: Spawner) { | |||
| 49 | config.rcc.mux = ClockSrc::PLL1_R; | 49 | config.rcc.mux = ClockSrc::PLL1_R; |
| 50 | config.rcc.pll = Some(Pll { | 50 | config.rcc.pll = Some(Pll { |
| 51 | // 80Mhz clock (16 / 1 * 10 / 2) | 51 | // 80Mhz clock (16 / 1 * 10 / 2) |
| 52 | source: PLLSource::HSI, | 52 | source: PllSource::HSI, |
| 53 | prediv: PllPreDiv::DIV1, | 53 | prediv: PllPreDiv::DIV1, |
| 54 | mul: PllMul::MUL10, | 54 | mul: PllMul::MUL10, |
| 55 | divp: None, | 55 | divp: None, |