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authorxoviat <[email protected]>2023-09-08 18:20:58 -0500
committerxoviat <[email protected]>2023-09-08 18:20:58 -0500
commit11a78fb1e4885604b6819253f97c20762fc0a23b (patch)
treec6fe875df02fc7b1762ebcf753b606f73a067a35 /examples/stm32wl/src
parent48154e18bf0a32e3fcba6359195df4f7e91bf5d0 (diff)
rcc: more cleanup
Diffstat (limited to 'examples/stm32wl/src')
-rw-r--r--examples/stm32wl/src/bin/lora_lorawan.rs2
-rw-r--r--examples/stm32wl/src/bin/random.rs2
-rw-r--r--examples/stm32wl/src/bin/rtc.rs1
3 files changed, 2 insertions, 3 deletions
diff --git a/examples/stm32wl/src/bin/lora_lorawan.rs b/examples/stm32wl/src/bin/lora_lorawan.rs
index 2c9c98861..230df4752 100644
--- a/examples/stm32wl/src/bin/lora_lorawan.rs
+++ b/examples/stm32wl/src/bin/lora_lorawan.rs
@@ -33,7 +33,7 @@ bind_interrupts!(struct Irqs{
33async fn main(_spawner: Spawner) { 33async fn main(_spawner: Spawner) {
34 let mut config = embassy_stm32::Config::default(); 34 let mut config = embassy_stm32::Config::default();
35 config.rcc.mux = embassy_stm32::rcc::ClockSrc::HSE32; 35 config.rcc.mux = embassy_stm32::rcc::ClockSrc::HSE32;
36 config.rcc.enable_lsi = true; // enable RNG 36 config.rcc.rtc_mux = embassy_stm32::rcc::RtcClockSource::LSI;
37 let p = embassy_stm32::init(config); 37 let p = embassy_stm32::init(config);
38 38
39 pac::RCC.ccipr().modify(|w| w.set_rngsel(0b01)); 39 pac::RCC.ccipr().modify(|w| w.set_rngsel(0b01));
diff --git a/examples/stm32wl/src/bin/random.rs b/examples/stm32wl/src/bin/random.rs
index 592e65f40..18eeac4fa 100644
--- a/examples/stm32wl/src/bin/random.rs
+++ b/examples/stm32wl/src/bin/random.rs
@@ -16,7 +16,7 @@ bind_interrupts!(struct Irqs{
16async fn main(_spawner: Spawner) { 16async fn main(_spawner: Spawner) {
17 let mut config = embassy_stm32::Config::default(); 17 let mut config = embassy_stm32::Config::default();
18 config.rcc.mux = embassy_stm32::rcc::ClockSrc::HSE32; 18 config.rcc.mux = embassy_stm32::rcc::ClockSrc::HSE32;
19 config.rcc.enable_lsi = true; //Needed for RNG to work 19 config.rcc.rtc_mux = embassy_stm32::rcc::RtcClockSource::LSI;
20 20
21 let p = embassy_stm32::init(config); 21 let p = embassy_stm32::init(config);
22 pac::RCC.ccipr().modify(|w| { 22 pac::RCC.ccipr().modify(|w| {
diff --git a/examples/stm32wl/src/bin/rtc.rs b/examples/stm32wl/src/bin/rtc.rs
index 2be6c7b93..e123425a0 100644
--- a/examples/stm32wl/src/bin/rtc.rs
+++ b/examples/stm32wl/src/bin/rtc.rs
@@ -17,7 +17,6 @@ async fn main(_spawner: Spawner) {
17 let mut config = Config::default(); 17 let mut config = Config::default();
18 config.rcc.mux = ClockSrc::HSE32; 18 config.rcc.mux = ClockSrc::HSE32;
19 config.rcc.rtc_mux = RtcClockSource::LSE; 19 config.rcc.rtc_mux = RtcClockSource::LSE;
20 config.rcc.enable_rtc_apb = true;
21 embassy_stm32::init(config) 20 embassy_stm32::init(config)
22 }; 21 };
23 info!("Hello World!"); 22 info!("Hello World!");