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authorDario Nieuwenhuis <[email protected]>2023-10-09 02:48:22 +0200
committerDario Nieuwenhuis <[email protected]>2023-10-09 02:48:22 +0200
commit6186fe08070c5f497d72586640db287193b41894 (patch)
treeaaef02d5344086bde66725a853851546961520fa /examples
parentc4cff0b79bc54634db9d0fa24a24add49b7ec7fe (diff)
stm32/rcc: use PLL enums from PAC.
Diffstat (limited to 'examples')
-rw-r--r--examples/stm32f2/src/bin/pll.rs6
-rw-r--r--examples/stm32g4/src/bin/adc.rs6
-rw-r--r--examples/stm32g4/src/bin/pll.rs6
-rw-r--r--examples/stm32g4/src/bin/usb_serial.rs8
-rw-r--r--examples/stm32h5/src/bin/eth.rs12
-rw-r--r--examples/stm32h5/src/bin/usb_serial.rs10
-rw-r--r--examples/stm32h7/src/bin/adc.rs14
-rw-r--r--examples/stm32h7/src/bin/camera.rs8
-rw-r--r--examples/stm32h7/src/bin/dac.rs14
-rw-r--r--examples/stm32h7/src/bin/dac_dma.rs14
-rw-r--r--examples/stm32h7/src/bin/eth.rs6
-rw-r--r--examples/stm32h7/src/bin/eth_client.rs6
-rw-r--r--examples/stm32h7/src/bin/fmc.rs8
-rw-r--r--examples/stm32h7/src/bin/low_level_timer_api.rs8
-rw-r--r--examples/stm32h7/src/bin/pwm.rs6
-rw-r--r--examples/stm32h7/src/bin/sdmmc.rs8
-rw-r--r--examples/stm32h7/src/bin/spi.rs8
-rw-r--r--examples/stm32h7/src/bin/spi_dma.rs8
-rw-r--r--examples/stm32h7/src/bin/usb_serial.rs6
-rw-r--r--examples/stm32l4/src/bin/rng.rs10
-rw-r--r--examples/stm32l4/src/bin/rtc.rs8
-rw-r--r--examples/stm32l4/src/bin/spe_adin1110_http_server.rs8
-rw-r--r--examples/stm32l4/src/bin/usb_serial.rs2
-rw-r--r--examples/stm32l5/src/bin/rng.rs10
-rw-r--r--examples/stm32l5/src/bin/usb_ethernet.rs2
-rw-r--r--examples/stm32l5/src/bin/usb_hid_mouse.rs2
-rw-r--r--examples/stm32l5/src/bin/usb_serial.rs2
-rw-r--r--examples/stm32u5/src/bin/usb_serial.rs6
28 files changed, 108 insertions, 104 deletions
diff --git a/examples/stm32f2/src/bin/pll.rs b/examples/stm32f2/src/bin/pll.rs
index 894937614..62aaa9800 100644
--- a/examples/stm32f2/src/bin/pll.rs
+++ b/examples/stm32f2/src/bin/pll.rs
@@ -7,7 +7,7 @@ use core::convert::TryFrom;
7use defmt::*; 7use defmt::*;
8use embassy_executor::Spawner; 8use embassy_executor::Spawner;
9use embassy_stm32::rcc::{ 9use embassy_stm32::rcc::{
10 APBPrescaler, ClockSrc, HSEConfig, HSESrc, PLL48Div, PLLConfig, PLLMainDiv, PLLMul, PLLPreDiv, PLLSrc, 10 APBPrescaler, ClockSrc, HSEConfig, HSESrc, PLLConfig, PLLMul, PLLPDiv, PLLPreDiv, PLLQDiv, PLLSrc,
11}; 11};
12use embassy_stm32::time::Hertz; 12use embassy_stm32::time::Hertz;
13use embassy_stm32::Config; 13use embassy_stm32::Config;
@@ -32,9 +32,9 @@ async fn main(_spawner: Spawner) {
32 // 1 MHz PLL input * 240 = 240 MHz PLL VCO 32 // 1 MHz PLL input * 240 = 240 MHz PLL VCO
33 mul: unwrap!(PLLMul::try_from(240)), 33 mul: unwrap!(PLLMul::try_from(240)),
34 // 240 MHz PLL VCO / 2 = 120 MHz main PLL output 34 // 240 MHz PLL VCO / 2 = 120 MHz main PLL output
35 main_div: PLLMainDiv::Div2, 35 p_div: PLLPDiv::DIV2,
36 // 240 MHz PLL VCO / 5 = 48 MHz PLL48 output 36 // 240 MHz PLL VCO / 5 = 48 MHz PLL48 output
37 pll48_div: unwrap!(PLL48Div::try_from(5)), 37 q_div: PLLQDiv::DIV5,
38 }; 38 };
39 // System clock comes from PLL (= the 120 MHz main PLL output) 39 // System clock comes from PLL (= the 120 MHz main PLL output)
40 config.rcc.mux = ClockSrc::PLL; 40 config.rcc.mux = ClockSrc::PLL;
diff --git a/examples/stm32g4/src/bin/adc.rs b/examples/stm32g4/src/bin/adc.rs
index a792748bc..da9b18a0e 100644
--- a/examples/stm32g4/src/bin/adc.rs
+++ b/examples/stm32g4/src/bin/adc.rs
@@ -16,12 +16,12 @@ async fn main(_spawner: Spawner) {
16 16
17 config.rcc.pll = Some(Pll { 17 config.rcc.pll = Some(Pll {
18 source: PllSrc::HSI16, 18 source: PllSrc::HSI16,
19 prediv_m: PllM::Div4, 19 prediv_m: PllM::DIV4,
20 mul_n: PllN::Mul85, 20 mul_n: PllN::MUL85,
21 div_p: None, 21 div_p: None,
22 div_q: None, 22 div_q: None,
23 // Main system clock at 170 MHz 23 // Main system clock at 170 MHz
24 div_r: Some(PllR::Div2), 24 div_r: Some(PllR::DIV2),
25 }); 25 });
26 26
27 config.rcc.adc12_clock_source = AdcClockSource::SysClk; 27 config.rcc.adc12_clock_source = AdcClockSource::SysClk;
diff --git a/examples/stm32g4/src/bin/pll.rs b/examples/stm32g4/src/bin/pll.rs
index ef7d4800c..f8159cb53 100644
--- a/examples/stm32g4/src/bin/pll.rs
+++ b/examples/stm32g4/src/bin/pll.rs
@@ -15,12 +15,12 @@ async fn main(_spawner: Spawner) {
15 15
16 config.rcc.pll = Some(Pll { 16 config.rcc.pll = Some(Pll {
17 source: PllSrc::HSI16, 17 source: PllSrc::HSI16,
18 prediv_m: PllM::Div4, 18 prediv_m: PllM::DIV4,
19 mul_n: PllN::Mul85, 19 mul_n: PllN::MUL85,
20 div_p: None, 20 div_p: None,
21 div_q: None, 21 div_q: None,
22 // Main system clock at 170 MHz 22 // Main system clock at 170 MHz
23 div_r: Some(PllR::Div2), 23 div_r: Some(PllR::DIV2),
24 }); 24 });
25 25
26 config.rcc.mux = ClockSrc::PLL; 26 config.rcc.mux = ClockSrc::PLL;
diff --git a/examples/stm32g4/src/bin/usb_serial.rs b/examples/stm32g4/src/bin/usb_serial.rs
index 77cfa67d3..9099b609a 100644
--- a/examples/stm32g4/src/bin/usb_serial.rs
+++ b/examples/stm32g4/src/bin/usb_serial.rs
@@ -25,16 +25,16 @@ async fn main(_spawner: Spawner) {
25 // Change this to `false` to use the HSE clock source for the USB. This example assumes an 8MHz HSE. 25 // Change this to `false` to use the HSE clock source for the USB. This example assumes an 8MHz HSE.
26 const USE_HSI48: bool = true; 26 const USE_HSI48: bool = true;
27 27
28 let pllq_div = if USE_HSI48 { None } else { Some(PllQ::Div6) }; 28 let pllq_div = if USE_HSI48 { None } else { Some(PllQ::DIV6) };
29 29
30 config.rcc.pll = Some(Pll { 30 config.rcc.pll = Some(Pll {
31 source: PllSrc::HSE(Hertz(8_000_000)), 31 source: PllSrc::HSE(Hertz(8_000_000)),
32 prediv_m: PllM::Div2, 32 prediv_m: PllM::DIV2,
33 mul_n: PllN::Mul72, 33 mul_n: PllN::MUL72,
34 div_p: None, 34 div_p: None,
35 div_q: pllq_div, 35 div_q: pllq_div,
36 // Main system clock at 144 MHz 36 // Main system clock at 144 MHz
37 div_r: Some(PllR::Div2), 37 div_r: Some(PllR::DIV2),
38 }); 38 });
39 39
40 config.rcc.mux = ClockSrc::PLL; 40 config.rcc.mux = ClockSrc::PLL;
diff --git a/examples/stm32h5/src/bin/eth.rs b/examples/stm32h5/src/bin/eth.rs
index 4e92d0647..2f4454761 100644
--- a/examples/stm32h5/src/bin/eth.rs
+++ b/examples/stm32h5/src/bin/eth.rs
@@ -9,7 +9,9 @@ use embassy_net::{Ipv4Address, Stack, StackResources};
9use embassy_stm32::eth::generic_smi::GenericSMI; 9use embassy_stm32::eth::generic_smi::GenericSMI;
10use embassy_stm32::eth::{Ethernet, PacketQueue}; 10use embassy_stm32::eth::{Ethernet, PacketQueue};
11use embassy_stm32::peripherals::ETH; 11use embassy_stm32::peripherals::ETH;
12use embassy_stm32::rcc::{AHBPrescaler, APBPrescaler, Hse, HseMode, Pll, PllSource, Sysclk, VoltageScale}; 12use embassy_stm32::rcc::{
13 AHBPrescaler, APBPrescaler, Hse, HseMode, Pll, PllDiv, PllMul, PllPreDiv, PllSource, Sysclk, VoltageScale,
14};
13use embassy_stm32::rng::Rng; 15use embassy_stm32::rng::Rng;
14use embassy_stm32::time::Hertz; 16use embassy_stm32::time::Hertz;
15use embassy_stm32::{bind_interrupts, eth, peripherals, rng, Config}; 17use embassy_stm32::{bind_interrupts, eth, peripherals, rng, Config};
@@ -42,10 +44,10 @@ async fn main(spawner: Spawner) -> ! {
42 }); 44 });
43 config.rcc.pll1 = Some(Pll { 45 config.rcc.pll1 = Some(Pll {
44 source: PllSource::Hse, 46 source: PllSource::Hse,
45 prediv: 2, 47 prediv: PllPreDiv::DIV2,
46 mul: 125, 48 mul: PllMul::MUL125,
47 divp: Some(2), 49 divp: Some(PllDiv::DIV2),
48 divq: Some(2), 50 divq: Some(PllDiv::DIV2),
49 divr: None, 51 divr: None,
50 }); 52 });
51 config.rcc.ahb_pre = AHBPrescaler::DIV1; 53 config.rcc.ahb_pre = AHBPrescaler::DIV1;
diff --git a/examples/stm32h5/src/bin/usb_serial.rs b/examples/stm32h5/src/bin/usb_serial.rs
index cbe540a06..3b3c38e17 100644
--- a/examples/stm32h5/src/bin/usb_serial.rs
+++ b/examples/stm32h5/src/bin/usb_serial.rs
@@ -4,7 +4,9 @@
4 4
5use defmt::{panic, *}; 5use defmt::{panic, *};
6use embassy_executor::Spawner; 6use embassy_executor::Spawner;
7use embassy_stm32::rcc::{AHBPrescaler, APBPrescaler, Hse, HseMode, Pll, PllSource, Sysclk, VoltageScale}; 7use embassy_stm32::rcc::{
8 AHBPrescaler, APBPrescaler, Hse, HseMode, Pll, PllDiv, PllMul, PllPreDiv, PllSource, Sysclk, VoltageScale,
9};
8use embassy_stm32::time::Hertz; 10use embassy_stm32::time::Hertz;
9use embassy_stm32::usb::{Driver, Instance}; 11use embassy_stm32::usb::{Driver, Instance};
10use embassy_stm32::{bind_interrupts, pac, peripherals, usb, Config}; 12use embassy_stm32::{bind_interrupts, pac, peripherals, usb, Config};
@@ -29,9 +31,9 @@ async fn main(_spawner: Spawner) {
29 }); 31 });
30 config.rcc.pll1 = Some(Pll { 32 config.rcc.pll1 = Some(Pll {
31 source: PllSource::Hse, 33 source: PllSource::Hse,
32 prediv: 2, 34 prediv: PllPreDiv::DIV2,
33 mul: 125, 35 mul: PllMul::MUL125,
34 divp: Some(2), // 250mhz 36 divp: Some(PllDiv::DIV2), // 250mhz
35 divq: None, 37 divq: None,
36 divr: None, 38 divr: None,
37 }); 39 });
diff --git a/examples/stm32h7/src/bin/adc.rs b/examples/stm32h7/src/bin/adc.rs
index 77922d4bc..7859b86db 100644
--- a/examples/stm32h7/src/bin/adc.rs
+++ b/examples/stm32h7/src/bin/adc.rs
@@ -18,16 +18,16 @@ async fn main(_spawner: Spawner) {
18 config.rcc.csi = true; 18 config.rcc.csi = true;
19 config.rcc.pll_src = PllSource::Hsi; 19 config.rcc.pll_src = PllSource::Hsi;
20 config.rcc.pll1 = Some(Pll { 20 config.rcc.pll1 = Some(Pll {
21 prediv: 4, 21 prediv: PllPreDiv::DIV4,
22 mul: 50, 22 mul: PllMul::MUL50,
23 divp: Some(2), 23 divp: Some(PllDiv::DIV2),
24 divq: Some(8), // SPI1 cksel defaults to pll1_q 24 divq: Some(PllDiv::DIV8), // SPI1 cksel defaults to pll1_q
25 divr: None, 25 divr: None,
26 }); 26 });
27 config.rcc.pll2 = Some(Pll { 27 config.rcc.pll2 = Some(Pll {
28 prediv: 4, 28 prediv: PllPreDiv::DIV4,
29 mul: 50, 29 mul: PllMul::MUL50,
30 divp: Some(8), // 100mhz 30 divp: Some(PllDiv::DIV8), // 100mhz
31 divq: None, 31 divq: None,
32 divr: None, 32 divr: None,
33 }); 33 });
diff --git a/examples/stm32h7/src/bin/camera.rs b/examples/stm32h7/src/bin/camera.rs
index 64ca65a02..40ef16cfc 100644
--- a/examples/stm32h7/src/bin/camera.rs
+++ b/examples/stm32h7/src/bin/camera.rs
@@ -32,10 +32,10 @@ async fn main(_spawner: Spawner) {
32 config.rcc.csi = true; 32 config.rcc.csi = true;
33 config.rcc.pll_src = PllSource::Hsi; 33 config.rcc.pll_src = PllSource::Hsi;
34 config.rcc.pll1 = Some(Pll { 34 config.rcc.pll1 = Some(Pll {
35 prediv: 4, 35 prediv: PllPreDiv::DIV4,
36 mul: 50, 36 mul: PllMul::MUL50,
37 divp: Some(2), 37 divp: Some(PllDiv::DIV2),
38 divq: Some(8), // 100mhz 38 divq: Some(PllDiv::DIV8), // 100mhz
39 divr: None, 39 divr: None,
40 }); 40 });
41 config.rcc.sys = Sysclk::Pll1P; // 400 Mhz 41 config.rcc.sys = Sysclk::Pll1P; // 400 Mhz
diff --git a/examples/stm32h7/src/bin/dac.rs b/examples/stm32h7/src/bin/dac.rs
index 93df7a319..821221897 100644
--- a/examples/stm32h7/src/bin/dac.rs
+++ b/examples/stm32h7/src/bin/dac.rs
@@ -20,16 +20,16 @@ fn main() -> ! {
20 config.rcc.csi = true; 20 config.rcc.csi = true;
21 config.rcc.pll_src = PllSource::Hsi; 21 config.rcc.pll_src = PllSource::Hsi;
22 config.rcc.pll1 = Some(Pll { 22 config.rcc.pll1 = Some(Pll {
23 prediv: 4, 23 prediv: PllPreDiv::DIV4,
24 mul: 50, 24 mul: PllMul::MUL50,
25 divp: Some(2), 25 divp: Some(PllDiv::DIV2),
26 divq: Some(8), // SPI1 cksel defaults to pll1_q 26 divq: Some(PllDiv::DIV8), // 100mhz
27 divr: None, 27 divr: None,
28 }); 28 });
29 config.rcc.pll2 = Some(Pll { 29 config.rcc.pll2 = Some(Pll {
30 prediv: 4, 30 prediv: PllPreDiv::DIV4,
31 mul: 50, 31 mul: PllMul::MUL50,
32 divp: Some(8), // 100mhz 32 divp: Some(PllDiv::DIV8), // 100mhz
33 divq: None, 33 divq: None,
34 divr: None, 34 divr: None,
35 }); 35 });
diff --git a/examples/stm32h7/src/bin/dac_dma.rs b/examples/stm32h7/src/bin/dac_dma.rs
index 8c921abca..933641ae4 100644
--- a/examples/stm32h7/src/bin/dac_dma.rs
+++ b/examples/stm32h7/src/bin/dac_dma.rs
@@ -28,16 +28,16 @@ async fn main(spawner: Spawner) {
28 config.rcc.csi = true; 28 config.rcc.csi = true;
29 config.rcc.pll_src = PllSource::Hsi; 29 config.rcc.pll_src = PllSource::Hsi;
30 config.rcc.pll1 = Some(Pll { 30 config.rcc.pll1 = Some(Pll {
31 prediv: 4, 31 prediv: PllPreDiv::DIV4,
32 mul: 50, 32 mul: PllMul::MUL50,
33 divp: Some(2), 33 divp: Some(PllDiv::DIV2),
34 divq: Some(8), // SPI1 cksel defaults to pll1_q 34 divq: Some(PllDiv::DIV8), // 100mhz
35 divr: None, 35 divr: None,
36 }); 36 });
37 config.rcc.pll2 = Some(Pll { 37 config.rcc.pll2 = Some(Pll {
38 prediv: 4, 38 prediv: PllPreDiv::DIV4,
39 mul: 50, 39 mul: PllMul::MUL50,
40 divp: Some(8), // 100mhz 40 divp: Some(PllDiv::DIV8), // 100mhz
41 divq: None, 41 divq: None,
42 divr: None, 42 divr: None,
43 }); 43 });
diff --git a/examples/stm32h7/src/bin/eth.rs b/examples/stm32h7/src/bin/eth.rs
index 1b5d71ed3..a6603d507 100644
--- a/examples/stm32h7/src/bin/eth.rs
+++ b/examples/stm32h7/src/bin/eth.rs
@@ -39,9 +39,9 @@ async fn main(spawner: Spawner) -> ! {
39 config.rcc.hsi48 = true; // needed for RNG 39 config.rcc.hsi48 = true; // needed for RNG
40 config.rcc.pll_src = PllSource::Hsi; 40 config.rcc.pll_src = PllSource::Hsi;
41 config.rcc.pll1 = Some(Pll { 41 config.rcc.pll1 = Some(Pll {
42 prediv: 4, 42 prediv: PllPreDiv::DIV4,
43 mul: 50, 43 mul: PllMul::MUL50,
44 divp: Some(2), 44 divp: Some(PllDiv::DIV2),
45 divq: None, 45 divq: None,
46 divr: None, 46 divr: None,
47 }); 47 });
diff --git a/examples/stm32h7/src/bin/eth_client.rs b/examples/stm32h7/src/bin/eth_client.rs
index 3abd31c73..596de2f40 100644
--- a/examples/stm32h7/src/bin/eth_client.rs
+++ b/examples/stm32h7/src/bin/eth_client.rs
@@ -40,9 +40,9 @@ async fn main(spawner: Spawner) -> ! {
40 config.rcc.hsi48 = true; // needed for RNG 40 config.rcc.hsi48 = true; // needed for RNG
41 config.rcc.pll_src = PllSource::Hsi; 41 config.rcc.pll_src = PllSource::Hsi;
42 config.rcc.pll1 = Some(Pll { 42 config.rcc.pll1 = Some(Pll {
43 prediv: 4, 43 prediv: PllPreDiv::DIV4,
44 mul: 50, 44 mul: PllMul::MUL50,
45 divp: Some(2), 45 divp: Some(PllDiv::DIV2),
46 divq: None, 46 divq: None,
47 divr: None, 47 divr: None,
48 }); 48 });
diff --git a/examples/stm32h7/src/bin/fmc.rs b/examples/stm32h7/src/bin/fmc.rs
index de0b351df..7ae87b02c 100644
--- a/examples/stm32h7/src/bin/fmc.rs
+++ b/examples/stm32h7/src/bin/fmc.rs
@@ -18,10 +18,10 @@ async fn main(_spawner: Spawner) {
18 config.rcc.csi = true; 18 config.rcc.csi = true;
19 config.rcc.pll_src = PllSource::Hsi; 19 config.rcc.pll_src = PllSource::Hsi;
20 config.rcc.pll1 = Some(Pll { 20 config.rcc.pll1 = Some(Pll {
21 prediv: 4, 21 prediv: PllPreDiv::DIV4,
22 mul: 50, 22 mul: PllMul::MUL50,
23 divp: Some(2), 23 divp: Some(PllDiv::DIV2),
24 divq: Some(8), // 100mhz 24 divq: Some(PllDiv::DIV8), // 100mhz
25 divr: None, 25 divr: None,
26 }); 26 });
27 config.rcc.sys = Sysclk::Pll1P; // 400 Mhz 27 config.rcc.sys = Sysclk::Pll1P; // 400 Mhz
diff --git a/examples/stm32h7/src/bin/low_level_timer_api.rs b/examples/stm32h7/src/bin/low_level_timer_api.rs
index a1e955c39..f4fa06909 100644
--- a/examples/stm32h7/src/bin/low_level_timer_api.rs
+++ b/examples/stm32h7/src/bin/low_level_timer_api.rs
@@ -22,10 +22,10 @@ async fn main(_spawner: Spawner) {
22 config.rcc.hsi48 = true; // needed for RNG 22 config.rcc.hsi48 = true; // needed for RNG
23 config.rcc.pll_src = PllSource::Hsi; 23 config.rcc.pll_src = PllSource::Hsi;
24 config.rcc.pll1 = Some(Pll { 24 config.rcc.pll1 = Some(Pll {
25 prediv: 4, 25 prediv: PllPreDiv::DIV4,
26 mul: 50, 26 mul: PllMul::MUL50,
27 divp: Some(2), 27 divp: Some(PllDiv::DIV2),
28 divq: Some(8), // 100 Mhz 28 divq: Some(PllDiv::DIV8), // 100mhz
29 divr: None, 29 divr: None,
30 }); 30 });
31 config.rcc.sys = Sysclk::Pll1P; // 400 Mhz 31 config.rcc.sys = Sysclk::Pll1P; // 400 Mhz
diff --git a/examples/stm32h7/src/bin/pwm.rs b/examples/stm32h7/src/bin/pwm.rs
index 5c8e57aa2..37e4c92cc 100644
--- a/examples/stm32h7/src/bin/pwm.rs
+++ b/examples/stm32h7/src/bin/pwm.rs
@@ -21,9 +21,9 @@ async fn main(_spawner: Spawner) {
21 config.rcc.csi = true; 21 config.rcc.csi = true;
22 config.rcc.pll_src = PllSource::Hsi; 22 config.rcc.pll_src = PllSource::Hsi;
23 config.rcc.pll1 = Some(Pll { 23 config.rcc.pll1 = Some(Pll {
24 prediv: 4, 24 prediv: PllPreDiv::DIV4,
25 mul: 50, 25 mul: PllMul::MUL50,
26 divp: Some(2), 26 divp: Some(PllDiv::DIV2),
27 divq: None, 27 divq: None,
28 divr: None, 28 divr: None,
29 }); 29 });
diff --git a/examples/stm32h7/src/bin/sdmmc.rs b/examples/stm32h7/src/bin/sdmmc.rs
index 752aefdf7..ecb8d6542 100644
--- a/examples/stm32h7/src/bin/sdmmc.rs
+++ b/examples/stm32h7/src/bin/sdmmc.rs
@@ -22,10 +22,10 @@ async fn main(_spawner: Spawner) -> ! {
22 config.rcc.csi = true; 22 config.rcc.csi = true;
23 config.rcc.pll_src = PllSource::Hsi; 23 config.rcc.pll_src = PllSource::Hsi;
24 config.rcc.pll1 = Some(Pll { 24 config.rcc.pll1 = Some(Pll {
25 prediv: 4, 25 prediv: PllPreDiv::DIV4,
26 mul: 50, 26 mul: PllMul::MUL50,
27 divp: Some(2), 27 divp: Some(PllDiv::DIV2),
28 divq: Some(4), // default clock chosen by SDMMCSEL. 200 Mhz 28 divq: Some(PllDiv::DIV4), // default clock chosen by SDMMCSEL. 200 Mhz
29 divr: None, 29 divr: None,
30 }); 30 });
31 config.rcc.sys = Sysclk::Pll1P; // 400 Mhz 31 config.rcc.sys = Sysclk::Pll1P; // 400 Mhz
diff --git a/examples/stm32h7/src/bin/spi.rs b/examples/stm32h7/src/bin/spi.rs
index 9fe46f031..f128d4a56 100644
--- a/examples/stm32h7/src/bin/spi.rs
+++ b/examples/stm32h7/src/bin/spi.rs
@@ -44,10 +44,10 @@ fn main() -> ! {
44 config.rcc.csi = true; 44 config.rcc.csi = true;
45 config.rcc.pll_src = PllSource::Hsi; 45 config.rcc.pll_src = PllSource::Hsi;
46 config.rcc.pll1 = Some(Pll { 46 config.rcc.pll1 = Some(Pll {
47 prediv: 4, 47 prediv: PllPreDiv::DIV4,
48 mul: 50, 48 mul: PllMul::MUL50,
49 divp: Some(2), 49 divp: Some(PllDiv::DIV2),
50 divq: Some(4), // used by SPI3. 100Mhz. 50 divq: Some(PllDiv::DIV8), // used by SPI3. 100Mhz.
51 divr: None, 51 divr: None,
52 }); 52 });
53 config.rcc.sys = Sysclk::Pll1P; // 400 Mhz 53 config.rcc.sys = Sysclk::Pll1P; // 400 Mhz
diff --git a/examples/stm32h7/src/bin/spi_dma.rs b/examples/stm32h7/src/bin/spi_dma.rs
index 88d65d5be..d4c0bcdbd 100644
--- a/examples/stm32h7/src/bin/spi_dma.rs
+++ b/examples/stm32h7/src/bin/spi_dma.rs
@@ -40,10 +40,10 @@ fn main() -> ! {
40 config.rcc.csi = true; 40 config.rcc.csi = true;
41 config.rcc.pll_src = PllSource::Hsi; 41 config.rcc.pll_src = PllSource::Hsi;
42 config.rcc.pll1 = Some(Pll { 42 config.rcc.pll1 = Some(Pll {
43 prediv: 4, 43 prediv: PllPreDiv::DIV4,
44 mul: 50, 44 mul: PllMul::MUL50,
45 divp: Some(2), 45 divp: Some(PllDiv::DIV2),
46 divq: Some(4), // used by SPI3. 100Mhz. 46 divq: Some(PllDiv::DIV8), // used by SPI3. 100Mhz.
47 divr: None, 47 divr: None,
48 }); 48 });
49 config.rcc.sys = Sysclk::Pll1P; // 400 Mhz 49 config.rcc.sys = Sysclk::Pll1P; // 400 Mhz
diff --git a/examples/stm32h7/src/bin/usb_serial.rs b/examples/stm32h7/src/bin/usb_serial.rs
index 14de43568..c1e5144be 100644
--- a/examples/stm32h7/src/bin/usb_serial.rs
+++ b/examples/stm32h7/src/bin/usb_serial.rs
@@ -28,9 +28,9 @@ async fn main(_spawner: Spawner) {
28 config.rcc.hsi48 = true; // needed for USB 28 config.rcc.hsi48 = true; // needed for USB
29 config.rcc.pll_src = PllSource::Hsi; 29 config.rcc.pll_src = PllSource::Hsi;
30 config.rcc.pll1 = Some(Pll { 30 config.rcc.pll1 = Some(Pll {
31 prediv: 4, 31 prediv: PllPreDiv::DIV4,
32 mul: 50, 32 mul: PllMul::MUL50,
33 divp: Some(2), 33 divp: Some(PllDiv::DIV2),
34 divq: None, 34 divq: None,
35 divr: None, 35 divr: None,
36 }); 36 });
diff --git a/examples/stm32l4/src/bin/rng.rs b/examples/stm32l4/src/bin/rng.rs
index 806e49f59..d0208d8a3 100644
--- a/examples/stm32l4/src/bin/rng.rs
+++ b/examples/stm32l4/src/bin/rng.rs
@@ -4,7 +4,7 @@
4 4
5use defmt::*; 5use defmt::*;
6use embassy_executor::Spawner; 6use embassy_executor::Spawner;
7use embassy_stm32::rcc::{ClockSrc, PLLClkDiv, PLLMul, PLLSource, PLLSrcDiv}; 7use embassy_stm32::rcc::{ClockSrc, PLLSource, PllMul, PllPreDiv, PllQDiv, PllRDiv};
8use embassy_stm32::rng::Rng; 8use embassy_stm32::rng::Rng;
9use embassy_stm32::{bind_interrupts, peripherals, rng, Config}; 9use embassy_stm32::{bind_interrupts, peripherals, rng, Config};
10use {defmt_rtt as _, panic_probe as _}; 10use {defmt_rtt as _, panic_probe as _};
@@ -19,10 +19,10 @@ async fn main(_spawner: Spawner) {
19 // 72Mhz clock (16 / 1 * 18 / 4) 19 // 72Mhz clock (16 / 1 * 18 / 4)
20 config.rcc.mux = ClockSrc::PLL( 20 config.rcc.mux = ClockSrc::PLL(
21 PLLSource::HSI16, 21 PLLSource::HSI16,
22 PLLClkDiv::Div4, 22 PllRDiv::DIV4,
23 PLLSrcDiv::Div1, 23 PllPreDiv::DIV1,
24 PLLMul::Mul18, 24 PllMul::MUL18,
25 Some(PLLClkDiv::Div6), // 48Mhz (16 / 1 * 18 / 6) 25 Some(PllQDiv::DIV6), // 48Mhz (16 / 1 * 18 / 6)
26 ); 26 );
27 let p = embassy_stm32::init(config); 27 let p = embassy_stm32::init(config);
28 28
diff --git a/examples/stm32l4/src/bin/rtc.rs b/examples/stm32l4/src/bin/rtc.rs
index eb1eed012..7e2b8c783 100644
--- a/examples/stm32l4/src/bin/rtc.rs
+++ b/examples/stm32l4/src/bin/rtc.rs
@@ -5,7 +5,7 @@
5use chrono::{NaiveDate, NaiveDateTime}; 5use chrono::{NaiveDate, NaiveDateTime};
6use defmt::*; 6use defmt::*;
7use embassy_executor::Spawner; 7use embassy_executor::Spawner;
8use embassy_stm32::rcc::{self, ClockSrc, PLLClkDiv, PLLMul, PLLSource, PLLSrcDiv}; 8use embassy_stm32::rcc::{self, ClockSrc, PLLSource, PllMul, PllPreDiv, PllRDiv};
9use embassy_stm32::rtc::{Rtc, RtcConfig}; 9use embassy_stm32::rtc::{Rtc, RtcConfig};
10use embassy_stm32::time::Hertz; 10use embassy_stm32::time::Hertz;
11use embassy_stm32::Config; 11use embassy_stm32::Config;
@@ -18,9 +18,9 @@ async fn main(_spawner: Spawner) {
18 let mut config = Config::default(); 18 let mut config = Config::default();
19 config.rcc.mux = ClockSrc::PLL( 19 config.rcc.mux = ClockSrc::PLL(
20 PLLSource::HSE(Hertz::mhz(8)), 20 PLLSource::HSE(Hertz::mhz(8)),
21 PLLClkDiv::Div2, 21 PllRDiv::DIV2,
22 PLLSrcDiv::Div1, 22 PllPreDiv::DIV1,
23 PLLMul::Mul20, 23 PllMul::MUL20,
24 None, 24 None,
25 ); 25 );
26 config.rcc.lse = Some(Hertz(32_768)); 26 config.rcc.lse = Some(Hertz(32_768));
diff --git a/examples/stm32l4/src/bin/spe_adin1110_http_server.rs b/examples/stm32l4/src/bin/spe_adin1110_http_server.rs
index ba4a9d230..8db89be24 100644
--- a/examples/stm32l4/src/bin/spe_adin1110_http_server.rs
+++ b/examples/stm32l4/src/bin/spe_adin1110_http_server.rs
@@ -49,7 +49,7 @@ use embassy_net_adin1110::{self, Device, Runner, ADIN1110};
49use embedded_hal_bus::spi::ExclusiveDevice; 49use embedded_hal_bus::spi::ExclusiveDevice;
50use hal::gpio::Pull; 50use hal::gpio::Pull;
51use hal::i2c::Config as I2C_Config; 51use hal::i2c::Config as I2C_Config;
52use hal::rcc::{ClockSrc, PLLClkDiv, PLLMul, PLLSource, PLLSrcDiv}; 52use hal::rcc::{ClockSrc, PLLSource, PllMul, PllPreDiv, PllRDiv};
53use hal::spi::{Config as SPI_Config, Spi}; 53use hal::spi::{Config as SPI_Config, Spi};
54use hal::time::Hertz; 54use hal::time::Hertz;
55 55
@@ -80,9 +80,9 @@ async fn main(spawner: Spawner) {
80 // 80MHz highest frequency for flash 0 wait. 80 // 80MHz highest frequency for flash 0 wait.
81 config.rcc.mux = ClockSrc::PLL( 81 config.rcc.mux = ClockSrc::PLL(
82 PLLSource::HSE(Hertz(8_000_000)), 82 PLLSource::HSE(Hertz(8_000_000)),
83 PLLClkDiv::Div2, 83 PllRDiv::DIV2,
84 PLLSrcDiv::Div1, 84 PllPreDiv::DIV1,
85 PLLMul::Mul20, 85 PllMul::MUL20,
86 None, 86 None,
87 ); 87 );
88 config.rcc.hsi48 = true; // needed for rng 88 config.rcc.hsi48 = true; // needed for rng
diff --git a/examples/stm32l4/src/bin/usb_serial.rs b/examples/stm32l4/src/bin/usb_serial.rs
index 410d6891b..dc0d98ad4 100644
--- a/examples/stm32l4/src/bin/usb_serial.rs
+++ b/examples/stm32l4/src/bin/usb_serial.rs
@@ -23,7 +23,7 @@ async fn main(_spawner: Spawner) {
23 info!("Hello World!"); 23 info!("Hello World!");
24 24
25 let mut config = Config::default(); 25 let mut config = Config::default();
26 config.rcc.mux = ClockSrc::PLL(PLLSource::HSI16, PLLClkDiv::Div2, PLLSrcDiv::Div1, PLLMul::Mul10, None); 26 config.rcc.mux = ClockSrc::PLL(PLLSource::HSI16, PllRDiv::DIV2, PllPreDiv::DIV1, PllMul::MUL10, None);
27 config.rcc.hsi48 = true; 27 config.rcc.hsi48 = true;
28 28
29 let p = embassy_stm32::init(config); 29 let p = embassy_stm32::init(config);
diff --git a/examples/stm32l5/src/bin/rng.rs b/examples/stm32l5/src/bin/rng.rs
index 9549d64d8..cc3c99b57 100644
--- a/examples/stm32l5/src/bin/rng.rs
+++ b/examples/stm32l5/src/bin/rng.rs
@@ -4,7 +4,7 @@
4 4
5use defmt::*; 5use defmt::*;
6use embassy_executor::Spawner; 6use embassy_executor::Spawner;
7use embassy_stm32::rcc::{ClockSrc, PLLClkDiv, PLLMul, PLLSource, PLLSrcDiv}; 7use embassy_stm32::rcc::{ClockSrc, PLLSource, PllMul, PllPreDiv, PllQDiv, PllRDiv};
8use embassy_stm32::rng::Rng; 8use embassy_stm32::rng::Rng;
9use embassy_stm32::{bind_interrupts, peripherals, rng, Config}; 9use embassy_stm32::{bind_interrupts, peripherals, rng, Config};
10use {defmt_rtt as _, panic_probe as _}; 10use {defmt_rtt as _, panic_probe as _};
@@ -18,10 +18,10 @@ async fn main(_spawner: Spawner) {
18 let mut config = Config::default(); 18 let mut config = Config::default();
19 config.rcc.mux = ClockSrc::PLL( 19 config.rcc.mux = ClockSrc::PLL(
20 PLLSource::HSI16, 20 PLLSource::HSI16,
21 PLLClkDiv::Div2, 21 PllRDiv::DIV2,
22 PLLSrcDiv::Div1, 22 PllPreDiv::DIV1,
23 PLLMul::Mul8, 23 PllMul::MUL8,
24 Some(PLLClkDiv::Div2), 24 Some(PllQDiv::DIV2),
25 ); 25 );
26 let p = embassy_stm32::init(config); 26 let p = embassy_stm32::init(config);
27 27
diff --git a/examples/stm32l5/src/bin/usb_ethernet.rs b/examples/stm32l5/src/bin/usb_ethernet.rs
index 15b84761b..498147f9d 100644
--- a/examples/stm32l5/src/bin/usb_ethernet.rs
+++ b/examples/stm32l5/src/bin/usb_ethernet.rs
@@ -45,7 +45,7 @@ async fn net_task(stack: &'static Stack<Device<'static, MTU>>) -> ! {
45#[embassy_executor::main] 45#[embassy_executor::main]
46async fn main(spawner: Spawner) { 46async fn main(spawner: Spawner) {
47 let mut config = Config::default(); 47 let mut config = Config::default();
48 config.rcc.mux = ClockSrc::PLL(PLLSource::HSI16, PLLClkDiv::Div2, PLLSrcDiv::Div1, PLLMul::Mul10, None); 48 config.rcc.mux = ClockSrc::PLL(PLLSource::HSI16, PllRDiv::DIV2, PllPreDiv::DIV1, PllMul::MUL10, None);
49 config.rcc.hsi48 = true; 49 config.rcc.hsi48 = true;
50 let p = embassy_stm32::init(config); 50 let p = embassy_stm32::init(config);
51 51
diff --git a/examples/stm32l5/src/bin/usb_hid_mouse.rs b/examples/stm32l5/src/bin/usb_hid_mouse.rs
index 7e894e407..db6a9c76f 100644
--- a/examples/stm32l5/src/bin/usb_hid_mouse.rs
+++ b/examples/stm32l5/src/bin/usb_hid_mouse.rs
@@ -22,7 +22,7 @@ bind_interrupts!(struct Irqs {
22#[embassy_executor::main] 22#[embassy_executor::main]
23async fn main(_spawner: Spawner) { 23async fn main(_spawner: Spawner) {
24 let mut config = Config::default(); 24 let mut config = Config::default();
25 config.rcc.mux = ClockSrc::PLL(PLLSource::HSI16, PLLClkDiv::Div2, PLLSrcDiv::Div1, PLLMul::Mul10, None); 25 config.rcc.mux = ClockSrc::PLL(PLLSource::HSI16, PllRDiv::DIV2, PllPreDiv::DIV1, PllMul::MUL10, None);
26 config.rcc.hsi48 = true; 26 config.rcc.hsi48 = true;
27 let p = embassy_stm32::init(config); 27 let p = embassy_stm32::init(config);
28 28
diff --git a/examples/stm32l5/src/bin/usb_serial.rs b/examples/stm32l5/src/bin/usb_serial.rs
index 0c719560f..e19ecbf08 100644
--- a/examples/stm32l5/src/bin/usb_serial.rs
+++ b/examples/stm32l5/src/bin/usb_serial.rs
@@ -20,7 +20,7 @@ bind_interrupts!(struct Irqs {
20#[embassy_executor::main] 20#[embassy_executor::main]
21async fn main(_spawner: Spawner) { 21async fn main(_spawner: Spawner) {
22 let mut config = Config::default(); 22 let mut config = Config::default();
23 config.rcc.mux = ClockSrc::PLL(PLLSource::HSI16, PLLClkDiv::Div2, PLLSrcDiv::Div1, PLLMul::Mul10, None); 23 config.rcc.mux = ClockSrc::PLL(PLLSource::HSI16, PllRDiv::DIV2, PllPreDiv::DIV1, PllMul::MUL10, None);
24 config.rcc.hsi48 = true; 24 config.rcc.hsi48 = true;
25 let p = embassy_stm32::init(config); 25 let p = embassy_stm32::init(config);
26 26
diff --git a/examples/stm32u5/src/bin/usb_serial.rs b/examples/stm32u5/src/bin/usb_serial.rs
index 278bd30f0..9b2adb0ac 100644
--- a/examples/stm32u5/src/bin/usb_serial.rs
+++ b/examples/stm32u5/src/bin/usb_serial.rs
@@ -25,9 +25,9 @@ async fn main(_spawner: Spawner) {
25 let mut config = Config::default(); 25 let mut config = Config::default();
26 config.rcc.mux = ClockSrc::PLL1R(PllConfig { 26 config.rcc.mux = ClockSrc::PLL1R(PllConfig {
27 source: PllSrc::HSI16, 27 source: PllSrc::HSI16,
28 m: PllM::Div2, 28 m: Pllm::DIV2,
29 n: PllN::Mul10, 29 n: Plln::MUL10,
30 r: PllClkDiv::NotDivided, 30 r: Plldiv::DIV1,
31 }); 31 });
32 //config.rcc.mux = ClockSrc::MSI(MSIRange::Range48mhz); 32 //config.rcc.mux = ClockSrc::MSI(MSIRange::Range48mhz);
33 config.rcc.hsi48 = true; 33 config.rcc.hsi48 = true;
generated by cgit (git 2.34.1) at 2026-04-05 19:46:08 +0000