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| author | Dario Nieuwenhuis <[email protected]> | 2023-10-12 14:09:13 +0000 |
|---|---|---|
| committer | GitHub <[email protected]> | 2023-10-12 14:09:13 +0000 |
| commit | 66e399b5c61653f1f66cd3fd1592936e4085d6b5 (patch) | |
| tree | 57e19f5533b612a4911ba1cd33fce3bf95ea4344 /examples | |
| parent | 01eb1a73396002bf0a335f51d31328d21b32bb02 (diff) | |
| parent | 65f81a1f577f2f1b9de78246f2f8fd495a3b4354 (diff) | |
Merge pull request #2035 from pbert519/stm_reset_and_enable
STM32: combine RccPeripherals reset() and enable() to enable_and_reset()
Diffstat (limited to 'examples')
| -rw-r--r-- | examples/stm32h7/src/bin/dac_dma.rs | 4 | ||||
| -rw-r--r-- | examples/stm32h7/src/bin/low_level_timer_api.rs | 3 | ||||
| -rw-r--r-- | examples/stm32l4/src/bin/dac_dma.rs | 4 |
3 files changed, 5 insertions, 6 deletions
diff --git a/examples/stm32h7/src/bin/dac_dma.rs b/examples/stm32h7/src/bin/dac_dma.rs index 933641ae4..334986a05 100644 --- a/examples/stm32h7/src/bin/dac_dma.rs +++ b/examples/stm32h7/src/bin/dac_dma.rs | |||
| @@ -79,7 +79,7 @@ async fn dac_task1(mut dac: Dac1Type) { | |||
| 79 | dac.select_trigger(embassy_stm32::dac::Ch1Trigger::Tim6).unwrap(); | 79 | dac.select_trigger(embassy_stm32::dac::Ch1Trigger::Tim6).unwrap(); |
| 80 | dac.enable_channel().unwrap(); | 80 | dac.enable_channel().unwrap(); |
| 81 | 81 | ||
| 82 | TIM6::enable(); | 82 | TIM6::enable_and_reset(); |
| 83 | TIM6::regs().arr().modify(|w| w.set_arr(reload as u16 - 1)); | 83 | TIM6::regs().arr().modify(|w| w.set_arr(reload as u16 - 1)); |
| 84 | TIM6::regs().cr2().modify(|w| w.set_mms(Mms::UPDATE)); | 84 | TIM6::regs().cr2().modify(|w| w.set_mms(Mms::UPDATE)); |
| 85 | TIM6::regs().cr1().modify(|w| { | 85 | TIM6::regs().cr1().modify(|w| { |
| @@ -118,7 +118,7 @@ async fn dac_task2(mut dac: Dac2Type) { | |||
| 118 | error!("Reload value {} below threshold!", reload); | 118 | error!("Reload value {} below threshold!", reload); |
| 119 | } | 119 | } |
| 120 | 120 | ||
| 121 | TIM7::enable(); | 121 | TIM7::enable_and_reset(); |
| 122 | TIM7::regs().arr().modify(|w| w.set_arr(reload as u16 - 1)); | 122 | TIM7::regs().arr().modify(|w| w.set_arr(reload as u16 - 1)); |
| 123 | TIM7::regs().cr2().modify(|w| w.set_mms(Mms::UPDATE)); | 123 | TIM7::regs().cr2().modify(|w| w.set_mms(Mms::UPDATE)); |
| 124 | TIM7::regs().cr1().modify(|w| { | 124 | TIM7::regs().cr1().modify(|w| { |
diff --git a/examples/stm32h7/src/bin/low_level_timer_api.rs b/examples/stm32h7/src/bin/low_level_timer_api.rs index f4fa06909..5841efb24 100644 --- a/examples/stm32h7/src/bin/low_level_timer_api.rs +++ b/examples/stm32h7/src/bin/low_level_timer_api.rs | |||
| @@ -73,8 +73,7 @@ impl<'d, T: CaptureCompare32bitInstance> SimplePwm32<'d, T> { | |||
| 73 | ) -> Self { | 73 | ) -> Self { |
| 74 | into_ref!(tim, ch1, ch2, ch3, ch4); | 74 | into_ref!(tim, ch1, ch2, ch3, ch4); |
| 75 | 75 | ||
| 76 | T::enable(); | 76 | T::enable_and_reset(); |
| 77 | <T as embassy_stm32::rcc::low_level::RccPeripheral>::reset(); | ||
| 78 | 77 | ||
| 79 | ch1.set_speed(Speed::VeryHigh); | 78 | ch1.set_speed(Speed::VeryHigh); |
| 80 | ch1.set_as_af(ch1.af_num(), AFType::OutputPushPull); | 79 | ch1.set_as_af(ch1.af_num(), AFType::OutputPushPull); |
diff --git a/examples/stm32l4/src/bin/dac_dma.rs b/examples/stm32l4/src/bin/dac_dma.rs index c27cc03e1..98f37f906 100644 --- a/examples/stm32l4/src/bin/dac_dma.rs +++ b/examples/stm32l4/src/bin/dac_dma.rs | |||
| @@ -51,7 +51,7 @@ async fn dac_task1(mut dac: Dac1Type) { | |||
| 51 | dac.select_trigger(embassy_stm32::dac::Ch1Trigger::Tim6).unwrap(); | 51 | dac.select_trigger(embassy_stm32::dac::Ch1Trigger::Tim6).unwrap(); |
| 52 | dac.enable_channel().unwrap(); | 52 | dac.enable_channel().unwrap(); |
| 53 | 53 | ||
| 54 | TIM6::enable(); | 54 | TIM6::enable_and_reset(); |
| 55 | TIM6::regs().arr().modify(|w| w.set_arr(reload as u16 - 1)); | 55 | TIM6::regs().arr().modify(|w| w.set_arr(reload as u16 - 1)); |
| 56 | TIM6::regs().cr2().modify(|w| w.set_mms(Mms::UPDATE)); | 56 | TIM6::regs().cr2().modify(|w| w.set_mms(Mms::UPDATE)); |
| 57 | TIM6::regs().cr1().modify(|w| { | 57 | TIM6::regs().cr1().modify(|w| { |
| @@ -90,7 +90,7 @@ async fn dac_task2(mut dac: Dac2Type) { | |||
| 90 | error!("Reload value {} below threshold!", reload); | 90 | error!("Reload value {} below threshold!", reload); |
| 91 | } | 91 | } |
| 92 | 92 | ||
| 93 | TIM7::enable(); | 93 | TIM7::enable_and_reset(); |
| 94 | TIM7::regs().arr().modify(|w| w.set_arr(reload as u16 - 1)); | 94 | TIM7::regs().arr().modify(|w| w.set_arr(reload as u16 - 1)); |
| 95 | TIM7::regs().cr2().modify(|w| w.set_mms(Mms::UPDATE)); | 95 | TIM7::regs().cr2().modify(|w| w.set_mms(Mms::UPDATE)); |
| 96 | TIM7::regs().cr1().modify(|w| { | 96 | TIM7::regs().cr1().modify(|w| { |
