Merge pull request #2069 from embassy-rs/rcc-no-spaghetti

stm32/rcc: add better support for L4/L4+ differences.

5 files changed, 5 insertions, 5 deletions

diff --git a/examples/stm32l4/src/bin/adc.rs b/examples/stm32l4/src/bin/adc.rs
index 1771e5202..3d0c623fd 100644
--- a/examples/stm32l4/src/bin/adc.rs
+++ b/examples/stm32l4/src/bin/adc.rs
@@ -13,7 +13,7 @@ fn main() -> ! {
     info!("Hello World!");
 
     pac::RCC.ccipr().modify(|w| {
-        w.set_adcsel(0b11);
+        w.set_adcsel(pac::rcc::vals::Adcsel::SYSCLK);
     });
     pac::RCC.ahb2enr().modify(|w| w.set_adcen(true));
 
diff --git a/examples/stm32l4/src/bin/rng.rs b/examples/stm32l4/src/bin/rng.rs
index 94251c12c..d184bcf77 100644
--- a/examples/stm32l4/src/bin/rng.rs
+++ b/examples/stm32l4/src/bin/rng.rs
@@ -18,8 +18,8 @@ async fn main(_spawner: Spawner) {
     let mut config = Config::default();
     config.rcc.mux = ClockSrc::PLL;
     config.rcc.hsi16 = true;
-    config.rcc.pll_src = PLLSource::HSI16;
     config.rcc.pll = Some(Pll {
+        source: PLLSource::HSI16,
         prediv: PllPreDiv::DIV1,
         mul: PllMul::MUL18,
         divp: None,
diff --git a/examples/stm32l4/src/bin/rtc.rs b/examples/stm32l4/src/bin/rtc.rs
index cd9f72ff3..a1b41f84a 100644
--- a/examples/stm32l4/src/bin/rtc.rs
+++ b/examples/stm32l4/src/bin/rtc.rs
@@ -17,8 +17,8 @@ async fn main(_spawner: Spawner) {
     let mut config = Config::default();
     config.rcc.mux = ClockSrc::PLL;
     config.rcc.hse = Some(Hertz::mhz(8));
-    config.rcc.pll_src = PLLSource::HSE;
     config.rcc.pll = Some(Pll {
+        source: PLLSource::HSE,
         prediv: PllPreDiv::DIV1,
         mul: PllMul::MUL20,
         divp: None,
diff --git a/examples/stm32l4/src/bin/spe_adin1110_http_server.rs b/examples/stm32l4/src/bin/spe_adin1110_http_server.rs
index c1a27cf83..278d65438 100644
--- a/examples/stm32l4/src/bin/spe_adin1110_http_server.rs
+++ b/examples/stm32l4/src/bin/spe_adin1110_http_server.rs
@@ -79,8 +79,8 @@ async fn main(spawner: Spawner) {
     // 80MHz highest frequency for flash 0 wait.
     config.rcc.mux = ClockSrc::PLL;
     config.rcc.hse = Some(Hertz::mhz(8));
-    config.rcc.pll_src = PLLSource::HSE;
     config.rcc.pll = Some(Pll {
+        source: PLLSource::HSE,
         prediv: PllPreDiv::DIV1,
         mul: PllMul::MUL20,
         divp: None,
diff --git a/examples/stm32l4/src/bin/usb_serial.rs b/examples/stm32l4/src/bin/usb_serial.rs
index 8f6eeef32..3785c6898 100644
--- a/examples/stm32l4/src/bin/usb_serial.rs
+++ b/examples/stm32l4/src/bin/usb_serial.rs
@@ -26,8 +26,8 @@ async fn main(_spawner: Spawner) {
     config.rcc.hsi48 = true;
     config.rcc.mux = ClockSrc::PLL;
     config.rcc.hsi16 = true;
-    config.rcc.pll_src = PLLSource::HSI16;
     config.rcc.pll = Some(Pll {
+        source: PLLSource::HSI16,
         prediv: PllPreDiv::DIV1,
         mul: PllMul::MUL10,
         divp: None,