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authorGerzain Mata <[email protected]>2025-07-25 18:46:09 -0700
committerGerzain Mata <[email protected]>2025-07-25 18:46:09 -0700
commit8733a5f56a310de3caba95246a0076fc33940d41 (patch)
treef4a829cd0a0e6c24042c0b7a0f9c8e045425856d /examples
parent75c1039aa11fa9a134511ce0988aefa088a0e6b0 (diff)
Fixed usb_hs_serial example
Diffstat (limited to 'examples')
-rw-r--r--examples/stm32wba/src/bin/usb_hs_serial.rs15
1 files changed, 7 insertions, 8 deletions
diff --git a/examples/stm32wba/src/bin/usb_hs_serial.rs b/examples/stm32wba/src/bin/usb_hs_serial.rs
index 393f8be6b..41440a940 100644
--- a/examples/stm32wba/src/bin/usb_hs_serial.rs
+++ b/examples/stm32wba/src/bin/usb_hs_serial.rs
@@ -5,8 +5,8 @@ use defmt::{panic, *};
5use defmt_rtt as _; // global logger 5use defmt_rtt as _; // global logger
6use embassy_executor::Spawner; 6use embassy_executor::Spawner;
7use embassy_futures::join::join; 7use embassy_futures::join::join;
8use embassy_stm32::rcc::{PllSource, PllPreDiv, PllMul, PllDiv}; 8use embassy_stm32::rcc::{mux, AHB5Prescaler, AHBPrescaler, APBPrescaler, Hse, HsePrescaler, Sysclk, VoltageScale};
9use embassy_stm32::rcc::{mux, AHBPrescaler, AHB5Prescaler, APBPrescaler, Hse, HsePrescaler, Sysclk, VoltageScale}; 9use embassy_stm32::rcc::{PllDiv, PllMul, PllPreDiv, PllSource};
10use embassy_stm32::usb::{Driver, Instance}; 10use embassy_stm32::usb::{Driver, Instance};
11use embassy_stm32::{bind_interrupts, peripherals, usb, Config}; 11use embassy_stm32::{bind_interrupts, peripherals, usb, Config};
12use embassy_usb::class::cdc_acm::{CdcAcmClass, State}; 12use embassy_usb::class::cdc_acm::{CdcAcmClass, State};
@@ -29,17 +29,16 @@ async fn main(_spawner: Spawner) {
29 // prescaler: HsePrescaler::DIV2, 29 // prescaler: HsePrescaler::DIV2,
30 // }); 30 // });
31 31
32
33 // Fine-tune PLL1 dividers/multipliers 32 // Fine-tune PLL1 dividers/multipliers
34 config.rcc.pll1 = Some(embassy_stm32::rcc::Pll { 33 config.rcc.pll1 = Some(embassy_stm32::rcc::Pll {
35 source: PllSource::HSI, 34 source: PllSource::HSI,
36 prediv: PllPreDiv::DIV1, // PLLM = 1 → HSI / 1 = 16 MHz 35 prediv: PllPreDiv::DIV1, // PLLM = 1 → HSI / 1 = 16 MHz
37 mul: PllMul::MUL30, // PLLN = 30 → 16 MHz * 30 = 480 MHz VCO 36 mul: PllMul::MUL30, // PLLN = 30 → 16 MHz * 30 = 480 MHz VCO
38 divr: Some(PllDiv::DIV5), // PLLR = 5 → 96 MHz (Sysclk) 37 divr: Some(PllDiv::DIV5), // PLLR = 5 → 96 MHz (Sysclk)
39 // divq: Some(PllDiv::DIV10), // PLLQ = 10 → 48 MHz (NOT USED) 38 // divq: Some(PllDiv::DIV10), // PLLQ = 10 → 48 MHz (NOT USED)
40 divq: None, 39 divq: None,
41 divp: Some(PllDiv::DIV30), // PLLP = 30 → 16 MHz (USBOTG) 40 divp: Some(PllDiv::DIV30), // PLLP = 30 → 16 MHz (USBOTG)
42 frac: Some(0), // Fractional part (enabled) 41 frac: Some(0), // Fractional part (enabled)
43 }); 42 });
44 43
45 config.rcc.ahb_pre = AHBPrescaler::DIV1; 44 config.rcc.ahb_pre = AHBPrescaler::DIV1;