stm32/rcc: unify f2 into f4/f7.

1 files changed, 29 insertions, 26 deletions

diff --git a/examples/stm32f2/src/bin/pll.rs b/examples/stm32f2/src/bin/pll.rs
index feec90016..aae7637dc 100644
--- a/examples/stm32f2/src/bin/pll.rs
+++ b/examples/stm32f2/src/bin/pll.rs
@@ -6,9 +6,6 @@ use core::convert::TryFrom;
 
 use defmt::*;
 use embassy_executor::Spawner;
-use embassy_stm32::rcc::{
-    APBPrescaler, ClockSrc, HSEConfig, HSESrc, Pll, PllMul, PllPDiv, PllPreDiv, PllQDiv, PllSource,
-};
 use embassy_stm32::time::Hertz;
 use embassy_stm32::Config;
 use embassy_time::Timer;
@@ -19,29 +16,35 @@ async fn main(_spawner: Spawner) {
     // Example config for maximum performance on a NUCLEO-F207ZG board
 
     let mut config = Config::default();
-    // By default, HSE on the board comes from a 8 MHz clock signal (not a crystal)
-    config.rcc.hse = Some(HSEConfig {
-        frequency: Hertz(8_000_000),
-        source: HSESrc::Bypass,
-    });
-    // PLL uses HSE as the clock source
-    config.rcc.pll_mux = PllSource::HSE;
-    config.rcc.pll = Pll {
-        // 8 MHz clock source / 8 = 1 MHz PLL input
-        pre_div: unwrap!(PllPreDiv::try_from(8)),
-        // 1 MHz PLL input * 240 = 240 MHz PLL VCO
-        mul: unwrap!(PllMul::try_from(240)),
-        // 240 MHz PLL VCO / 2 = 120 MHz main PLL output
-        divp: PllPDiv::DIV2,
-        // 240 MHz PLL VCO / 5 = 48 MHz PLL48 output
-        divq: PllQDiv::DIV5,
-    };
-    // System clock comes from PLL (= the 120 MHz main PLL output)
-    config.rcc.mux = ClockSrc::PLL;
-    // 120 MHz / 4 = 30 MHz APB1 frequency
-    config.rcc.apb1_pre = APBPrescaler::DIV4;
-    // 120 MHz / 2 = 60 MHz APB2 frequency
-    config.rcc.apb2_pre = APBPrescaler::DIV2;
+
+    {
+        use embassy_stm32::rcc::*;
+
+        // By default, HSE on the board comes from a 8 MHz clock signal (not a crystal)
+        config.rcc.hse = Some(Hse {
+            freq: Hertz(8_000_000),
+            mode: HseMode::Bypass,
+        });
+        // PLL uses HSE as the clock source
+        config.rcc.pll_src = PllSource::HSE;
+        config.rcc.pll = Some(Pll {
+            // 8 MHz clock source / 8 = 1 MHz PLL input
+            prediv: unwrap!(PllPreDiv::try_from(8)),
+            // 1 MHz PLL input * 240 = 240 MHz PLL VCO
+            mul: unwrap!(PllMul::try_from(240)),
+            // 240 MHz PLL VCO / 2 = 120 MHz main PLL output
+            divp: Some(PllPDiv::DIV2),
+            // 240 MHz PLL VCO / 5 = 48 MHz PLL48 output
+            divq: Some(PllQDiv::DIV5),
+            divr: None,
+        });
+        // System clock comes from PLL (= the 120 MHz main PLL output)
+        config.rcc.sys = Sysclk::PLL1_P;
+        // 120 MHz / 4 = 30 MHz APB1 frequency
+        config.rcc.apb1_pre = APBPrescaler::DIV4;
+        // 120 MHz / 2 = 60 MHz APB2 frequency
+        config.rcc.apb2_pre = APBPrescaler::DIV2;
+    }
 
     let _p = embassy_stm32::init(config);