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authorkbleeke <[email protected]>2023-03-02 19:02:32 +0100
committerkbleeke <[email protected]>2023-03-27 13:18:59 +0200
commitb58cc2aa239e4adba2c32462cc89133bb7d9f698 (patch)
tree236352d7335f0f81cea03a6e9c4646d643acceae /examples
parenta2272dda08a2d1625eef0b79fcd80afc8a1e174a (diff)
use irqs to wait for events
Diffstat (limited to 'examples')
-rw-r--r--examples/rpi-pico-w/src/main.rs6
-rw-r--r--examples/rpi-pico-w/src/pio.rs17
2 files changed, 19 insertions, 4 deletions
diff --git a/examples/rpi-pico-w/src/main.rs b/examples/rpi-pico-w/src/main.rs
index 434851378..97e2d6a60 100644
--- a/examples/rpi-pico-w/src/main.rs
+++ b/examples/rpi-pico-w/src/main.rs
@@ -227,4 +227,10 @@ impl cyw43::SpiBusCyw43 for MySpi {
227 self.read(read).await; 227 self.read(read).await;
228 self.cs.set_high(); 228 self.cs.set_high();
229 } 229 }
230
231 async fn wait_for_event(&mut self) {}
232
233 fn clear_event(&mut self) {}
234
235
230} 236}
diff --git a/examples/rpi-pico-w/src/pio.rs b/examples/rpi-pico-w/src/pio.rs
index 8017f4f44..6df227468 100644
--- a/examples/rpi-pico-w/src/pio.rs
+++ b/examples/rpi-pico-w/src/pio.rs
@@ -41,6 +41,9 @@ where
41 "in pins, 1 side 1" 41 "in pins, 1 side 1"
42 "jmp y-- lp2 side 0" 42 "jmp y-- lp2 side 0"
43 43
44 "wait 1 pin 0 side 0"
45 "irq 0 side 0"
46
44 ".wrap" 47 ".wrap"
45 ); 48 );
46 49
@@ -106,6 +109,7 @@ where
106 } 109 }
107 110
108 pub async fn write(&mut self, write: &[u32]) { 111 pub async fn write(&mut self, write: &[u32]) {
112 self.sm.set_enable(false);
109 let write_bits = write.len() * 32 - 1; 113 let write_bits = write.len() * 32 - 1;
110 let read_bits = 31; 114 let read_bits = 31;
111 115
@@ -124,11 +128,10 @@ where
124 let mut status = 0; 128 let mut status = 0;
125 self.sm.dma_pull(dma, slice::from_mut(&mut status)).await; 129 self.sm.dma_pull(dma, slice::from_mut(&mut status)).await;
126 defmt::trace!("{:#08x}", status); 130 defmt::trace!("{:#08x}", status);
127
128 self.sm.set_enable(false);
129 } 131 }
130 132
131 pub async fn cmd_read(&mut self, cmd: u32, read: &mut [u32]) { 133 pub async fn cmd_read(&mut self, cmd: u32, read: &mut [u32]) {
134 self.sm.set_enable(false);
132 let write_bits = 31; 135 let write_bits = 31;
133 let read_bits = read.len() * 32 - 1; 136 let read_bits = read.len() * 32 - 1;
134 137
@@ -144,8 +147,6 @@ where
144 147
145 self.sm.dma_push(dma.reborrow(), slice::from_ref(&cmd)).await; 148 self.sm.dma_push(dma.reborrow(), slice::from_ref(&cmd)).await;
146 self.sm.dma_pull(dma, read).await; 149 self.sm.dma_pull(dma, read).await;
147
148 self.sm.set_enable(false);
149 } 150 }
150} 151}
151 152
@@ -166,4 +167,12 @@ where
166 self.cmd_read(write, read).await; 167 self.cmd_read(write, read).await;
167 self.cs.set_high(); 168 self.cs.set_high();
168 } 169 }
170
171 async fn wait_for_event(&mut self) {
172 self.sm.wait_irq(0).await;
173 }
174
175 fn clear_event(&mut self) {
176 self.sm.clear_irq(0);
177 }
169} 178}