Merge #743

743: Add PLL config support for F2 r=Dirbaio a=Gekkio

- minor changes to make the F2 RCC API a bit more flexible
- low-level PLL config with assertions based on datasheet specs. It shouldn't be very difficult to later add a "reverse API" where you pass the clocks you want to a function and it generates a `PLLConfig` struct for you
- PLL API tested on my custom board with 12 MHz HSE as source for PLL to generate max clocks for SYSCLK/AHB/APB/APB1/PLL48
- the example *should* work but is untested since I don't have the Nucleo board :disappointed: 

Co-authored-by: Joonas Javanainen <[email protected]>

1 files changed, 56 insertions, 0 deletions

diff --git a/examples/stm32f2/src/bin/pll.rs b/examples/stm32f2/src/bin/pll.rs
new file mode 100644
index 000000000..4bd74f0bd
--- /dev/null
+++ b/examples/stm32f2/src/bin/pll.rs
@@ -0,0 +1,56 @@
+#![no_std]
+#![no_main]
+#![feature(type_alias_impl_trait)]
+
+use core::convert::TryFrom;
+use defmt::*;
+use embassy::executor::Spawner;
+use embassy::time::{Duration, Timer};
+use embassy_stm32::{
+    rcc::{
+        APBPrescaler, ClockSrc, HSEConfig, HSESrc, PLL48Div, PLLConfig, PLLMainDiv, PLLMul,
+        PLLPreDiv, PLLSrc,
+    },
+    time::Hertz,
+    Config, Peripherals,
+};
+
+use defmt_rtt as _; // global logger
+use panic_probe as _;
+
+// Example config for maximum performance on a NUCLEO-F207ZG board
+fn config() -> Config {
+    let mut config = Config::default();
+    // By default, HSE on the board comes from a 8 MHz clock signal (not a crystal)
+    config.rcc.hse = Some(HSEConfig {
+        frequency: Hertz(8_000_000),
+        source: HSESrc::Bypass,
+    });
+    // PLL uses HSE as the clock source
+    config.rcc.pll_mux = PLLSrc::HSE;
+    config.rcc.pll = PLLConfig {
+        // 8 MHz clock source / 8 = 1 MHz PLL input
+        pre_div: unwrap!(PLLPreDiv::try_from(8)),
+        // 1 MHz PLL input * 240 = 240 MHz PLL VCO
+        mul: unwrap!(PLLMul::try_from(240)),
+        // 240 MHz PLL VCO / 2 = 120 MHz main PLL output
+        main_div: PLLMainDiv::Div2,
+        // 240 MHz PLL VCO / 5 = 48 MHz PLL48 output
+        pll48_div: unwrap!(PLL48Div::try_from(5)),
+    };
+    // System clock comes from PLL (= the 120 MHz main PLL output)
+    config.rcc.mux = ClockSrc::PLL;
+    // 120 MHz / 4 = 30 MHz APB1 frequency
+    config.rcc.apb1_pre = APBPrescaler::Div4;
+    // 120 MHz / 2 = 60 MHz APB2 frequency
+    config.rcc.apb2_pre = APBPrescaler::Div2;
+    config
+}
+
+#[embassy::main(config = "config()")]
+async fn main(_spawner: Spawner, _p: Peripherals) {
+    loop {
+        Timer::after(Duration::from_millis(1000)).await;
+        info!("1s elapsed");
+    }
+}