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| author | Scott Mabin <[email protected]> | 2023-07-30 01:00:50 +0100 |
|---|---|---|
| committer | Scott Mabin <[email protected]> | 2023-07-30 01:00:53 +0100 |
| commit | e0ce7fcde7906fc219d294e858388e62ab107ec3 (patch) | |
| tree | 1fef483aa7a72fed8223d11c18166cc84eec4dd1 /examples | |
| parent | fcbfd224a729c38d5ff94d94a25321a819254630 (diff) | |
stm32f2 pll overflow with crystal
With a large enough HSE input frequency, the vco clock calculation will
overflow a u32. Therefore, in this specific case we have to use the
inner value and cast to u64 to ensure the mul isn't clipped before
applying the divider.
Diffstat (limited to 'examples')
0 files changed, 0 insertions, 0 deletions