aboutsummaryrefslogtreecommitdiff
path: root/examples
diff options
context:
space:
mode:
authorDario Nieuwenhuis <[email protected]>2023-12-25 14:26:00 +0000
committerGitHub <[email protected]>2023-12-25 14:26:00 +0000
commiteebfee189a592427423d3a3ad22132d59926a0e8 (patch)
tree04a904e569fb1870817aff3335958ef4e20b56e7 /examples
parent8b6c6c7df68088abc4a572a825a03e79c9b8694a (diff)
parentd90a97aa4c5977e3d071fb4ed94656e6666d965c (diff)
Merge pull request #2355 from eZioPan/update-metapac7
update metapac after stm32-data PR323
Diffstat (limited to 'examples')
-rw-r--r--examples/stm32f4/src/bin/ws2812_pwm_dma.rs3
-rw-r--r--examples/stm32h7/src/bin/dac_dma.rs6
-rw-r--r--examples/stm32l4/src/bin/dac_dma.rs6
3 files changed, 7 insertions, 8 deletions
diff --git a/examples/stm32f4/src/bin/ws2812_pwm_dma.rs b/examples/stm32f4/src/bin/ws2812_pwm_dma.rs
index cdce36f2e..4458b643f 100644
--- a/examples/stm32f4/src/bin/ws2812_pwm_dma.rs
+++ b/examples/stm32f4/src/bin/ws2812_pwm_dma.rs
@@ -21,7 +21,6 @@
21use embassy_executor::Spawner; 21use embassy_executor::Spawner;
22use embassy_stm32::gpio::OutputType; 22use embassy_stm32::gpio::OutputType;
23use embassy_stm32::pac; 23use embassy_stm32::pac;
24use embassy_stm32::pac::timer::vals::Ocpe;
25use embassy_stm32::time::khz; 24use embassy_stm32::time::khz;
26use embassy_stm32::timer::simple_pwm::{PwmPin, SimplePwm}; 25use embassy_stm32::timer::simple_pwm::{PwmPin, SimplePwm};
27use embassy_stm32::timer::{Channel, CountingMode}; 26use embassy_stm32::timer::{Channel, CountingMode};
@@ -94,7 +93,7 @@ async fn main(_spawner: Spawner) {
94 // keep output waveform integrity 93 // keep output waveform integrity
95 pac::TIM3 94 pac::TIM3
96 .ccmr_output(pwm_channel.index()) 95 .ccmr_output(pwm_channel.index())
97 .modify(|v| v.set_ocpe(0, Ocpe::ENABLED)); 96 .modify(|v| v.set_ocpe(0, true));
98 97
99 // make sure PWM output keep low on first start 98 // make sure PWM output keep low on first start
100 ws2812_pwm.set_duty(pwm_channel, 0); 99 ws2812_pwm.set_duty(pwm_channel, 0);
diff --git a/examples/stm32h7/src/bin/dac_dma.rs b/examples/stm32h7/src/bin/dac_dma.rs
index 1481dd967..8e5c41a43 100644
--- a/examples/stm32h7/src/bin/dac_dma.rs
+++ b/examples/stm32h7/src/bin/dac_dma.rs
@@ -4,7 +4,7 @@
4use defmt::*; 4use defmt::*;
5use embassy_executor::Spawner; 5use embassy_executor::Spawner;
6use embassy_stm32::dac::{DacCh1, DacCh2, ValueArray}; 6use embassy_stm32::dac::{DacCh1, DacCh2, ValueArray};
7use embassy_stm32::pac::timer::vals::{Mms, Opm}; 7use embassy_stm32::pac::timer::vals::Mms;
8use embassy_stm32::peripherals::{DAC1, DMA1_CH3, DMA1_CH4, TIM6, TIM7}; 8use embassy_stm32::peripherals::{DAC1, DMA1_CH3, DMA1_CH4, TIM6, TIM7};
9use embassy_stm32::rcc::low_level::RccPeripheral; 9use embassy_stm32::rcc::low_level::RccPeripheral;
10use embassy_stm32::time::Hertz; 10use embassy_stm32::time::Hertz;
@@ -78,7 +78,7 @@ async fn dac_task1(mut dac: DacCh1<'static, DAC1, DMA1_CH3>) {
78 TIM6::regs().arr().modify(|w| w.set_arr(reload as u16 - 1)); 78 TIM6::regs().arr().modify(|w| w.set_arr(reload as u16 - 1));
79 TIM6::regs().cr2().modify(|w| w.set_mms(Mms::UPDATE)); 79 TIM6::regs().cr2().modify(|w| w.set_mms(Mms::UPDATE));
80 TIM6::regs().cr1().modify(|w| { 80 TIM6::regs().cr1().modify(|w| {
81 w.set_opm(Opm::DISABLED); 81 w.set_opm(false);
82 w.set_cen(true); 82 w.set_cen(true);
83 }); 83 });
84 84
@@ -115,7 +115,7 @@ async fn dac_task2(mut dac: DacCh2<'static, DAC1, DMA1_CH4>) {
115 TIM7::regs().arr().modify(|w| w.set_arr(reload as u16 - 1)); 115 TIM7::regs().arr().modify(|w| w.set_arr(reload as u16 - 1));
116 TIM7::regs().cr2().modify(|w| w.set_mms(Mms::UPDATE)); 116 TIM7::regs().cr2().modify(|w| w.set_mms(Mms::UPDATE));
117 TIM7::regs().cr1().modify(|w| { 117 TIM7::regs().cr1().modify(|w| {
118 w.set_opm(Opm::DISABLED); 118 w.set_opm(false);
119 w.set_cen(true); 119 w.set_cen(true);
120 }); 120 });
121 121
diff --git a/examples/stm32l4/src/bin/dac_dma.rs b/examples/stm32l4/src/bin/dac_dma.rs
index 64c541caa..8e5098557 100644
--- a/examples/stm32l4/src/bin/dac_dma.rs
+++ b/examples/stm32l4/src/bin/dac_dma.rs
@@ -4,7 +4,7 @@
4use defmt::*; 4use defmt::*;
5use embassy_executor::Spawner; 5use embassy_executor::Spawner;
6use embassy_stm32::dac::{DacCh1, DacCh2, ValueArray}; 6use embassy_stm32::dac::{DacCh1, DacCh2, ValueArray};
7use embassy_stm32::pac::timer::vals::{Mms, Opm}; 7use embassy_stm32::pac::timer::vals::Mms;
8use embassy_stm32::peripherals::{DAC1, DMA1_CH3, DMA1_CH4, TIM6, TIM7}; 8use embassy_stm32::peripherals::{DAC1, DMA1_CH3, DMA1_CH4, TIM6, TIM7};
9use embassy_stm32::rcc::low_level::RccPeripheral; 9use embassy_stm32::rcc::low_level::RccPeripheral;
10use embassy_stm32::time::Hertz; 10use embassy_stm32::time::Hertz;
@@ -49,7 +49,7 @@ async fn dac_task1(mut dac: DacCh1<'static, DAC1, DMA1_CH3>) {
49 TIM6::regs().arr().modify(|w| w.set_arr(reload as u16 - 1)); 49 TIM6::regs().arr().modify(|w| w.set_arr(reload as u16 - 1));
50 TIM6::regs().cr2().modify(|w| w.set_mms(Mms::UPDATE)); 50 TIM6::regs().cr2().modify(|w| w.set_mms(Mms::UPDATE));
51 TIM6::regs().cr1().modify(|w| { 51 TIM6::regs().cr1().modify(|w| {
52 w.set_opm(Opm::DISABLED); 52 w.set_opm(false);
53 w.set_cen(true); 53 w.set_cen(true);
54 }); 54 });
55 55
@@ -86,7 +86,7 @@ async fn dac_task2(mut dac: DacCh2<'static, DAC1, DMA1_CH4>) {
86 TIM7::regs().arr().modify(|w| w.set_arr(reload as u16 - 1)); 86 TIM7::regs().arr().modify(|w| w.set_arr(reload as u16 - 1));
87 TIM7::regs().cr2().modify(|w| w.set_mms(Mms::UPDATE)); 87 TIM7::regs().cr2().modify(|w| w.set_mms(Mms::UPDATE));
88 TIM7::regs().cr1().modify(|w| { 88 TIM7::regs().cr1().modify(|w| {
89 w.set_opm(Opm::DISABLED); 89 w.set_opm(false);
90 w.set_cen(true); 90 w.set_cen(true);
91 }); 91 });
92 92