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| author | bors[bot] <26634292+bors[bot]@users.noreply.github.com> | 2022-03-09 01:47:52 +0000 |
|---|---|---|
| committer | GitHub <[email protected]> | 2022-03-09 01:47:52 +0000 |
| commit | 13247897b06e4abce8b76b7fa9a545b859cf80b6 (patch) | |
| tree | 545f2c4988c0836f9fe1dc3eb0e3846712ff7546 /rust-toolchain.toml | |
| parent | 3047098c554075d97a5def7acf0d248ea4df315b (diff) | |
| parent | 63030bf998b0787b421f30af4f75159e2cb5c99f (diff) | |
Merge #640
640: Skip EasyDMA slice location check for empty slices and copy data if necessary r=Dirbaio a=TilBlechschmidt
As discussed, this PR makes the following changes:
- Ignore pointer location of zero-length slices (fixes #631)
- Change default functions so they copy the tx buffer if it does not reside in RAM
- Introduce new variants for `write`, `transfer`, and their blocking versions which fails instead of copying
- Add documentation about the motivation behind all these variants
<img width="984" alt="image" src="https://user-images.githubusercontent.com/5037967/155415788-c2cd1055-9289-4004-959d-be3b1934a439.png">
Remaining TODOs:
- [x] Change copying behaviour for other peripherals
- [x] TWI
- [x] UART
- [x] Add module-level documentation regarding EasyDMA and `_from_ram` method variants
`@Dirbaio` it probably makes sense for you to review it now before I "copy" over the changes to the other two peripherals.
Co-authored-by: Til Blechschmidt <[email protected]>
Diffstat (limited to 'rust-toolchain.toml')
0 files changed, 0 insertions, 0 deletions