Wire up Lpuart pins (#43)

Allow the HAL lpuart driver to correctly configure pins as requested on init.

2 files changed, 10 insertions, 0 deletions

diff --git a/src/clocks/config.rs b/src/clocks/config.rs
index a517afcca..0563b8917 100644
--- a/src/clocks/config.rs
+++ b/src/clocks/config.rs
@@ -21,6 +21,11 @@ impl Div8 {
         Self(n)
     }
 
+    /// Divide by one, or no division
+    pub const fn no_div() -> Self {
+        Self(0)
+    }
+
     /// Store a specific divisor value that will divide the source
     /// by `n`. e.g. `Div8::from_divisor(1)` will divide the source
     /// by 1, and `Div8::from_divisor(256)` will divide the source
diff --git a/src/clocks/mod.rs b/src/clocks/mod.rs
index 948355079..cd6318c4b 100644
--- a/src/clocks/mod.rs
+++ b/src/clocks/mod.rs
@@ -928,6 +928,11 @@ pub(crate) mod gate {
     #[cfg(not(feature = "time"))]
     impl_cc_gate!(OSTIMER0, mrcc_glb_cc1, mrcc_glb_rst1, ostimer0, OsTimerConfig);
 
+    impl_cc_gate!(LPUART0, mrcc_glb_cc0, mrcc_glb_rst0, lpuart0, LpuartConfig);
+    impl_cc_gate!(LPUART1, mrcc_glb_cc0, mrcc_glb_rst0, lpuart1, LpuartConfig);
     impl_cc_gate!(LPUART2, mrcc_glb_cc0, mrcc_glb_rst0, lpuart2, LpuartConfig);
+    impl_cc_gate!(LPUART3, mrcc_glb_cc0, mrcc_glb_rst0, lpuart3, LpuartConfig);
+    impl_cc_gate!(LPUART4, mrcc_glb_cc0, mrcc_glb_rst0, lpuart4, LpuartConfig);
+    impl_cc_gate!(LPUART5, mrcc_glb_cc1, mrcc_glb_rst1, lpuart5, LpuartConfig);
     impl_cc_gate!(ADC1, mrcc_glb_cc1, mrcc_glb_rst1, adc1, AdcConfig);
 }