More work on examples

2 files changed, 18 insertions, 2 deletions

diff --git a/src/clocks/mod.rs b/src/clocks/mod.rs
index 24e118e38..e04f63b8e 100644
--- a/src/clocks/mod.rs
+++ b/src/clocks/mod.rs
@@ -79,6 +79,11 @@ pub unsafe fn assert_reset<G: Gate>() {
     G::assert_reset();
 }
 
+#[inline]
+pub unsafe fn is_reset_released<G: Gate>() -> bool {
+    G::is_reset_released()
+}
+
 /// Pulse a reset line (assert then release) with a short delay.
 #[inline]
 pub unsafe fn pulse_reset<G: Gate>() {
@@ -150,12 +155,15 @@ pub mod gate {
     use super::periph_helpers::{AdcConfig, LpuartConfig, OsTimerConfig};
     use super::*;
 
+    // These peripherals have no additional upstream clocks or configuration required
+    // other than enabling through the MRCC gate.
     impl_cc_gate!(PORT1, mrcc_glb_cc1, port1, NoConfig);
     impl_cc_gate!(PORT2, mrcc_glb_cc1, port2, NoConfig);
     impl_cc_gate!(PORT3, mrcc_glb_cc1, port3, NoConfig);
+    impl_cc_gate!(GPIO3, mrcc_glb_cc2, gpio3, NoConfig);
+
     impl_cc_gate!(OSTIMER0, mrcc_glb_cc1, ostimer0, OsTimerConfig);
     impl_cc_gate!(LPUART2, mrcc_glb_cc0, lpuart2, LpuartConfig);
-    impl_cc_gate!(GPIO3, mrcc_glb_cc2, gpio3, NoConfig);
     impl_cc_gate!(ADC1, mrcc_glb_cc1, adc1, AdcConfig);
 }
 
@@ -276,7 +284,7 @@ pub struct Clock {
     pub power: PoweredClock,
 }
 
-#[derive(Debug, Clone, Copy)]
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
 pub enum PoweredClock {
     NormalEnabledDeepSleepDisabled,
     AlwaysEnabled,
diff --git a/src/clocks/periph_helpers.rs b/src/clocks/periph_helpers.rs
index de767ef87..1657bd7eb 100644
--- a/src/clocks/periph_helpers.rs
+++ b/src/clocks/periph_helpers.rs
@@ -18,6 +18,11 @@ pub trait SPConfHelper {
 pub struct Div4(pub(super) u8);
 
 impl Div4 {
+    /// Divide by one, or no division
+    pub const fn no_div() -> Self {
+        Self(0)
+    }
+
     /// Store a "raw" divisor value that will divide the source by
     /// `(n + 1)`, e.g. `Div4::from_raw(0)` will divide the source
     /// by 1, and `Div4::from_raw(15)` will divide the source by
@@ -81,6 +86,7 @@ pub enum LpuartClockSel {
     None,
 }
 
+#[derive(Copy, Clone, Debug, PartialEq, Eq)]
 pub enum LpuartInstance {
     Lpuart0,
     Lpuart1,
@@ -102,6 +108,7 @@ pub struct LpuartConfig {
     pub(crate) instance: LpuartInstance,
 }
 
+#[derive(Copy, Clone, Debug, PartialEq, Eq)]
 pub enum OstimerClockSel {
     /// 16k clock, sourced from FRO16K (Vdd Core)
     Clk16kVddCore,
@@ -116,6 +123,7 @@ pub struct OsTimerConfig {
     pub source: OstimerClockSel,
 }
 
+#[derive(Copy, Clone, Debug, PartialEq, Eq)]
 pub enum AdcClockSel {
     FroLfDiv,
     FroHf,