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authorDaniel Bevenius <[email protected]>2022-09-23 09:35:54 +0200
committerDaniel Bevenius <[email protected]>2022-09-23 09:35:54 +0200
commit28bf4b7b6da0e0f6ce0878580363f135c7e7a879 (patch)
tree19b0e0fb9132f6d532b73b0d91046beae1ed9d16 /src
parent9db9333d0569ca8e86301f643e42abd37f3b7118 (diff)
Add const for IOCTL ANTDIV
Diffstat (limited to 'src')
-rw-r--r--src/lib.rs4
1 files changed, 3 insertions, 1 deletions
diff --git a/src/lib.rs b/src/lib.rs
index a6b26188d..f543f75e0 100644
--- a/src/lib.rs
+++ b/src/lib.rs
@@ -131,6 +131,7 @@ const IRQ_F3_INTR: u16 = 0x8000;
131 131
132const IOCTL_CMD_UP: u32 = 2; 132const IOCTL_CMD_UP: u32 = 2;
133const IOCTL_CMD_SET_SSID: u32 = 26; 133const IOCTL_CMD_SET_SSID: u32 = 26;
134const IOCTL_CMD_ANTDIV: u32 = 64;
134const IOCTL_CMD_SET_VAR: u32 = 263; 135const IOCTL_CMD_SET_VAR: u32 = 263;
135const IOCTL_CMD_GET_VAR: u32 = 262; 136const IOCTL_CMD_GET_VAR: u32 = 262;
136const IOCTL_CMD_SET_PASSPHRASE: u32 = 268; 137const IOCTL_CMD_SET_PASSPHRASE: u32 = 268;
@@ -310,7 +311,8 @@ impl<'a> Control<'a> {
310 // set country takes some time, next ioctls fail if we don't wait. 311 // set country takes some time, next ioctls fail if we don't wait.
311 Timer::after(Duration::from_millis(100)).await; 312 Timer::after(Duration::from_millis(100)).await;
312 313
313 self.ioctl_set_u32(64, 0, 0).await; // WLC_SET_ANTDIV 314 // Set antenna to chip antenna
315 self.ioctl_set_u32(IOCTL_CMD_ANTDIV, 0, 0).await;
314 316
315 self.set_iovar_u32("bus:txglom", 0).await; 317 self.set_iovar_u32("bus:txglom", 0).await;
316 Timer::after(Duration::from_millis(100)).await; 318 Timer::after(Duration::from_millis(100)).await;