Manually fix clippy lints

6 files changed, 33 insertions, 9 deletions

diff --git a/src/interrupt.rs b/src/interrupt.rs
index 09d7acbef..134ff03fd 100644
--- a/src/interrupt.rs
+++ b/src/interrupt.rs
@@ -2,6 +2,10 @@
 //! Type-level interrupt traits and bindings are provided by the
 //! `embassy_hal_internal::interrupt_mod!` macro via the generated module below.
 
+// TODO(AJM): As of 2025-11-13, we need to do a pass to ensure safety docs
+// are complete prior to release.
+#![allow(clippy::missing_safety_doc)]
+
 mod generated {
     embassy_hal_internal::interrupt_mod!(OS_EVENT, LPUART2, RTC, ADC1);
 }
diff --git a/src/lib.rs b/src/lib.rs
index fe27aadba..9899564d8 100644
--- a/src/lib.rs
+++ b/src/lib.rs
@@ -1,4 +1,7 @@
 #![no_std]
+// TODO(AJM): As of 2025-11-13, we need to do a pass to ensure safety docs
+// are complete prior to release.
+#![allow(clippy::missing_safety_doc)]
 
 pub mod clocks; // still provide clock helpers
 pub mod gpio;
diff --git a/src/lpuart/buffered.rs b/src/lpuart/buffered.rs
index 21b86ada9..a617c10a5 100644
--- a/src/lpuart/buffered.rs
+++ b/src/lpuart/buffered.rs
@@ -110,6 +110,7 @@ impl<'a> BufferedLpuart<'a> {
     }
 
     /// Create a new buffered LPUART with flexible pin configuration
+    #[allow(clippy::too_many_arguments)]
     pub fn new_with_pins<T: Instance>(
         _inner: Peri<'a, T>,
         tx_pin: Option<Peri<'a, impl TxPin<T>>>,
diff --git a/src/lpuart/mod.rs b/src/lpuart/mod.rs
index 854136144..35b531421 100644
--- a/src/lpuart/mod.rs
+++ b/src/lpuart/mod.rs
@@ -106,7 +106,8 @@ mod gpio {
                 impl GpioPin for super::lib::peripherals::$pin {}
 
                 impl From<super::lib::peripherals::$pin> for AnyPin {
-                    fn from(val: super::lib::peripherals::$pin) -> Self {
+                    // TODO: AJM: any reason we aren't using $pin?
+                    fn from(_val: super::lib::peripherals::$pin) -> Self {
                         AnyPin
                     }
                 }
@@ -242,7 +243,7 @@ pub fn configure_baudrate(regs: Regs, baudrate_bps: u32, clock: Clock) -> Result
     // Configure BAUD register
     regs.baud().modify(|_, w| unsafe {
         // Clear and set OSR
-        w.osr().bits((osr - 1));
+        w.osr().bits(osr - 1);
         // Clear and set SBR
         w.sbr().bits(sbr);
         // Set BOTHEDGE if OSR is between 4 and 7
diff --git a/src/rtc.rs b/src/rtc.rs
index afd46610e..facb9cf8c 100644
--- a/src/rtc.rs
+++ b/src/rtc.rs
@@ -109,18 +109,29 @@ pub fn convert_seconds_to_datetime(seconds: u32) -> RtcDateTime {
         };
     }
 
-    let mut days_per_month = [0u8, 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31];
-    if year.is_multiple_of(4) {
-        days_per_month[2] = 29;
-    }
+    let days_per_month = [
+        31,
+        if year.is_multiple_of(4) { 29 } else { 28 },
+        31,
+        30,
+        31,
+        30,
+        31,
+        31,
+        30,
+        31,
+        30,
+        31,
+    ];
 
     let mut month = 1;
-    for m in 1..=12 {
-        if days <= days_per_month[m] as u32 {
+    for (m, month_days) in days_per_month.iter().enumerate() {
+        let m = m + 1;
+        if days <= *month_days as u32 {
             month = m;
             break;
         } else {
-            days -= days_per_month[m] as u32;
+            days -= *month_days as u32;
         }
     }
 
diff --git a/src/uart.rs b/src/uart.rs
index cd504a6c6..3705959d3 100644
--- a/src/uart.rs
+++ b/src/uart.rs
@@ -1,6 +1,10 @@
 //! Minimal polling UART2 bring-up replicating MCUXpresso hello_world ordering.
 //! WARNING: This is a narrow implementation only for debug console (115200 8N1).
 
+// TODO(AJM): As of 2025-11-13, we need to do a pass to ensure safety docs
+// are complete prior to release.
+#![allow(clippy::missing_safety_doc)]
+
 use core::cell::RefCell;
 
 use cortex_m::interrupt::Mutex;