Plumb clocks changes to lpuart

5 files changed, 291 insertions, 174 deletions

diff --git a/src/clocks/mod.rs b/src/clocks/mod.rs
index ad48a9cf2..63a8fb64d 100644
--- a/src/clocks/mod.rs
+++ b/src/clocks/mod.rs
@@ -1,66 +1,157 @@
 //! Clock control helpers (no magic numbers, PAC field access only).
 //! Provides reusable gate abstractions for peripherals used by the examples.
+use core::cell::RefCell;
+
 use mcxa_pac::scg0::{
     firccsr::{FircFclkPeriphEn, FircSclkPeriphEn, Fircsten},
     sirccsr::{SircClkPeriphEn, Sircsten},
 };
+use periph_helpers::SPConfHelper;
 
 use crate::pac;
 pub mod periph_helpers;
 
-// /// Trait describing an AHB clock gate that can be toggled through MRCC.
-// pub trait Gate {
-//     /// Enable the clock gate.
-//     unsafe fn enable(mrcc: &pac::mrcc0::RegisterBlock);
+/// Trait describing an AHB clock gate that can be toggled through MRCC.
+pub trait Gate {
+    type MrccPeriphConfig: SPConfHelper;
 
-//     /// Return whether the clock gate is currently enabled.
-//     fn is_enabled(mrcc: &pac::mrcc0::RegisterBlock) -> bool;
-// }
+    /// Enable the clock gate.
+    unsafe fn enable_clock();
 
-// /// Enable a clock gate for the given peripheral set.
-// #[inline]
-// pub unsafe fn enable<G: Gate>(peripherals: &pac::Peripherals) {
-//     let mrcc = &peripherals.mrcc0;
-//     G::enable(mrcc);
-//     while !G::is_enabled(mrcc) {}
-//     core::arch::asm!("dsb sy; isb sy", options(nomem, nostack, preserves_flags));
-// }
+    /// Disable the clock gate.
+    unsafe fn disable_clock();
 
-// /// Check whether a gate is currently enabled.
-// #[inline]
-// pub fn is_enabled<G: Gate>(peripherals: &pac::Peripherals) -> bool {
-//     G::is_enabled(&peripherals.mrcc0)
-// }
+    /// Drive the peripheral into reset.
+    unsafe fn assert_reset();
 
-// macro_rules! impl_cc_gate {
-//     ($name:ident, $reg:ident, $field:ident) => {
-//         pub struct $name;
-
-//         impl Gate for $name {
-//             #[inline]
-//             unsafe fn enable(mrcc: &pac::mrcc0::RegisterBlock) {
-//                 mrcc.$reg().modify(|_, w| w.$field().enabled());
-//             }
-
-//             #[inline]
-//             fn is_enabled(mrcc: &pac::mrcc0::RegisterBlock) -> bool {
-//                 mrcc.$reg().read().$field().is_enabled()
-//             }
-//         }
-//     };
-// }
+    /// Drive the peripheral out of reset.
+    unsafe fn release_reset();
 
-// pub mod gate {
-//     use super::*;
+    /// Return whether the clock gate is currently enabled.
+    fn is_clock_enabled() -> bool;
 
-//     impl_cc_gate!(Port2, mrcc_glb_cc1, port2);
-//     impl_cc_gate!(Port3, mrcc_glb_cc1, port3);
-//     impl_cc_gate!(Ostimer0, mrcc_glb_cc1, ostimer0);
-//     impl_cc_gate!(Lpuart2, mrcc_glb_cc0, lpuart2);
-//     impl_cc_gate!(Gpio3, mrcc_glb_cc2, gpio3);
-//     impl_cc_gate!(Port1, mrcc_glb_cc1, port1);
-//     impl_cc_gate!(Adc1, mrcc_glb_cc1, adc1);
-// }
+    /// .
+    fn is_reset_released() -> bool;
+}
+
+#[inline]
+pub unsafe fn enable_and_reset<G: Gate>(cfg: &G::MrccPeriphConfig) -> Result<u32, ClockError> {
+    let freq = enable::<G>(cfg)?;
+    pulse_reset::<G>();
+    Ok(freq)
+}
+
+/// Enable a clock gate for the given peripheral set.
+#[inline]
+pub unsafe fn enable<G: Gate>(cfg: &G::MrccPeriphConfig) -> Result<u32, ClockError> {
+    G::enable_clock();
+    while !G::is_clock_enabled() {}
+    core::arch::asm!("dsb sy; isb sy", options(nomem, nostack, preserves_flags));
+
+    let freq = critical_section::with(|cs| {
+        let clocks = CLOCKS.borrow_ref(cs);
+        let clocks = clocks.as_ref().ok_or(ClockError::NeverInitialized)?;
+        cfg.post_enable_config(clocks)
+    });
+
+    freq.inspect_err(|_e| {
+        G::disable_clock();
+    })
+}
+
+pub unsafe fn disable<G: Gate>() {
+    G::disable_clock();
+}
+
+/// Check whether a gate is currently enabled.
+#[inline]
+pub fn is_clock_enabled<G: Gate>() -> bool {
+    G::is_clock_enabled()
+}
+
+/// Release a reset line for the given peripheral set.
+#[inline]
+pub unsafe fn release_reset<G: Gate>() {
+    G::release_reset();
+}
+
+/// Assert a reset line for the given peripheral set.
+#[inline]
+pub unsafe fn assert_reset<G: Gate>() {
+    G::assert_reset();
+}
+
+/// Pulse a reset line (assert then release) with a short delay.
+#[inline]
+pub unsafe fn pulse_reset<G: Gate>() {
+    G::assert_reset();
+    cortex_m::asm::nop();
+    cortex_m::asm::nop();
+    G::release_reset();
+}
+
+macro_rules! impl_cc_gate {
+    ($name:ident, $reg:ident, $field:ident, $config:ty) => {
+        impl Gate for crate::peripherals::$name {
+            type MrccPeriphConfig = $config;
+
+            #[inline]
+            unsafe fn enable_clock() {
+                let mrcc = unsafe { pac::Mrcc0::steal() };
+                mrcc.$reg().modify(|_, w| w.$field().enabled());
+            }
+
+            #[inline]
+            unsafe fn disable_clock() {
+                let mrcc = unsafe { pac::Mrcc0::steal() };
+                mrcc.$reg().modify(|_r, w| w.$field().disabled());
+            }
+
+            #[inline]
+            fn is_clock_enabled() -> bool {
+                let mrcc = unsafe { pac::Mrcc0::steal() };
+                mrcc.$reg().read().$field().is_enabled()
+            }
+
+            #[inline]
+            unsafe fn release_reset() {
+                let mrcc = unsafe { pac::Mrcc0::steal() };
+                mrcc.$reg().modify(|_, w| w.$field().enabled());
+            }
+
+            #[inline]
+            unsafe fn assert_reset() {
+                let mrcc = unsafe { pac::Mrcc0::steal() };
+                mrcc.$reg().modify(|_, w| w.$field().disabled());
+            }
+
+            #[inline]
+            fn is_reset_released() -> bool {
+                let mrcc = unsafe { pac::Mrcc0::steal() };
+                mrcc.$reg().read().$field().is_enabled()
+            }
+        }
+    };
+}
+
+pub struct UnimplementedConfig;
+impl SPConfHelper for UnimplementedConfig {
+    fn post_enable_config(&self, _clocks: &Clocks) -> Result<u32, ClockError> {
+        Err(ClockError::UnimplementedConfig)
+    }
+}
+
+pub mod gate {
+    use super::{periph_helpers::LpuartConfig, *};
+
+    impl_cc_gate!(PORT1, mrcc_glb_cc1, port1, UnimplementedConfig);
+    impl_cc_gate!(PORT2, mrcc_glb_cc1, port2, UnimplementedConfig);
+    impl_cc_gate!(PORT3, mrcc_glb_cc1, port3, UnimplementedConfig);
+    impl_cc_gate!(OSTIMER0, mrcc_glb_cc1, ostimer0, UnimplementedConfig);
+    impl_cc_gate!(LPUART2, mrcc_glb_cc0, lpuart2, LpuartConfig);
+    impl_cc_gate!(GPIO3, mrcc_glb_cc2, gpio3, UnimplementedConfig);
+    impl_cc_gate!(ADC1, mrcc_glb_cc1, adc1, UnimplementedConfig);
+}
 
 // /// Convenience helper enabling the PORT2 and LPUART2 gates required for the debug UART.
 // pub unsafe fn enable_uart2_port2(peripherals: &pac::Peripherals) {
@@ -113,20 +204,6 @@ pub mod periph_helpers;
 //     mrcc.mrcc_ostimer0_clksel().write(|w| w.mux().clkroot_1m());
 // }
 
-// pub unsafe fn init_fro16k(peripherals: &pac::Peripherals) {
-//     let vbat = &peripherals.vbat0;
-//     // Enable FRO16K oscillator
-//     vbat.froctla().modify(|_, w| w.fro_en().set_bit());
-
-//     // Lock the control register
-//     vbat.frolcka().modify(|_, w| w.lock().set_bit());
-
-//     // Enable clock outputs to both VSYS and VDD_CORE domains
-//     // Bit 0: clk_16k0 to VSYS domain
-//     // Bit 1: clk_16k1 to VDD_CORE domain
-//     vbat.froclke().modify(|_, w| unsafe { w.clke().bits(0x3) });
-// }
-
 // pub unsafe fn enable_adc(peripherals: &pac::Peripherals) {
 //     enable::<gate::Port1>(peripherals);
 //     enable::<gate::Adc1>(peripherals);
@@ -271,6 +348,7 @@ pub struct ClocksConfig {
     pub firc: Option<FircConfig>,
     // NOTE: I don't think we *can* disable the SIRC?
     pub sirc: SircConfig,
+    pub fro16k: Option<Fro16KConfig>,
 }
 
 // FIRC/FRO180M
@@ -340,17 +418,30 @@ pub struct Clocks {
     pub fro_lf_div: Option<Clock>,
     //
     // End FRO12M stuff
+
+    pub clk_16k_vsys: Option<Clock>,
+    pub clk_16k_vdd_core: Option<Clock>,
     pub main_clk: Option<Clock>,
     pub pll1_clk: Option<Clock>,
 }
 
-static CLOCKS: critical_section::Mutex<Option<Clocks>> = critical_section::Mutex::new(None);
+#[non_exhaustive]
+pub struct Fro16KConfig {
+    pub vsys_domain_active: bool,
+    pub vdd_core_domain_active: bool,
+}
+
+static CLOCKS: critical_section::Mutex<RefCell<Option<Clocks>>> = critical_section::Mutex::new(RefCell::new(None));
 
+#[derive(Debug, Copy, Clone, Eq, PartialEq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[non_exhaustive]
 pub enum ClockError {
+    NeverInitialized,
     AlreadyInitialized,
     BadConfig { clock: &'static str, reason: &'static str },
     NotImplemented { clock: &'static str },
+    UnimplementedConfig,
 }
 
 struct ClockOperator<'a> {
@@ -360,6 +451,7 @@ struct ClockOperator<'a> {
     _mrcc0: pac::Mrcc0,
     scg0: pac::Scg0,
     syscon: pac::Syscon,
+    vbat0: pac::Vbat0,
 }
 
 impl ClockOperator<'_> {
@@ -586,13 +678,52 @@ impl ClockOperator<'_> {
             });
         }
 
-        todo!()
+        Ok(())
+    }
+
+    fn configure_fro16k_clocks(&mut self) -> Result<(), ClockError> {
+        let Some(fro16k) = self.config.fro16k.as_ref() else {
+            return Ok(());
+        };
+        // Enable FRO16K oscillator
+        self.vbat0.froctla().modify(|_, w| w.fro_en().set_bit());
+
+        // Lock the control register
+        self.vbat0.frolcka().modify(|_, w| w.lock().set_bit());
+
+        let Fro16KConfig { vsys_domain_active, vdd_core_domain_active } = fro16k;
+
+        // Enable clock outputs to both VSYS and VDD_CORE domains
+        // Bit 0: clk_16k0 to VSYS domain
+        // Bit 1: clk_16k1 to VDD_CORE domain
+        //
+        // TODO: Define sub-fields for this register with a PAC patch?
+        let mut bits = 0;
+        if *vsys_domain_active {
+            bits |= 0b01;
+            self.clocks.clk_16k_vsys = Some(Clock {
+                frequency: 16_384,
+                power: PoweredClock::AlwaysEnabled,
+            });
+        }
+        if *vdd_core_domain_active {
+            bits |= 0b10;
+            self.clocks.clk_16k_vdd_core = Some(Clock {
+                frequency: 16_384,
+                power: PoweredClock::AlwaysEnabled,
+            });
+        }
+        self.vbat0.froclke().modify(|_r, w| {
+            unsafe { w.clke().bits(bits) }
+        });
+
+        Ok(())
     }
 }
 
 pub fn init(settings: ClocksConfig) -> Result<(), ClockError> {
     critical_section::with(|cs| {
-        if CLOCKS.borrow(cs).is_some() {
+        if CLOCKS.borrow_ref(cs).is_some() {
             Err(ClockError::AlreadyInitialized)
         } else {
             Ok(())
@@ -607,12 +738,20 @@ pub fn init(settings: ClocksConfig) -> Result<(), ClockError> {
         _mrcc0: unsafe { pac::Mrcc0::steal() },
         scg0: unsafe { pac::Scg0::steal() },
         syscon: unsafe { pac::Syscon::steal() },
+        vbat0: unsafe { pac::Vbat0::steal() },
     };
 
     operator.configure_firc_clocks()?;
     operator.configure_sirc_clocks()?;
+    operator.configure_fro16k_clocks()?;
     // TODO, everything downstream
 
+    critical_section::with(|cs| {
+        let mut clks = CLOCKS.borrow_ref_mut(cs);
+        assert!(clks.is_none(), "Clock setup race!");
+        *clks = Some(clocks);
+    });
+
     Ok(())
 }
 
@@ -621,7 +760,8 @@ pub fn init(settings: ClocksConfig) -> Result<(), ClockError> {
 /// NOTE: Clocks implements `Clone`,
 pub fn with_clocks<R: 'static, F: FnOnce(&Clocks) -> R>(f: F) -> Option<R> {
     critical_section::with(|cs| {
-        let c = CLOCKS.borrow(cs).as_ref()?;
+        let c = CLOCKS.borrow_ref(cs);
+        let c = c.as_ref()?;
         Some(f(c))
     })
 }
@@ -629,20 +769,32 @@ pub fn with_clocks<R: 'static, F: FnOnce(&Clocks) -> R>(f: F) -> Option<R> {
 impl Clocks {
     pub fn ensure_fro_lf_div_active(&self, at_level: &PoweredClock) -> Result<u32, ClockError> {
         let Some(clk) = self.fro_lf_div.as_ref() else {
-            return Err(ClockError::BadConfig { clock: "fro_lf_div", reason: "required but not active" });
+            return Err(ClockError::BadConfig {
+                clock: "fro_lf_div",
+                reason: "required but not active",
+            });
         };
         if !clk.power.meets_requirement_of(at_level) {
-            return Err(ClockError::BadConfig { clock: "fro_lf_div", reason: "not low power active" });
+            return Err(ClockError::BadConfig {
+                clock: "fro_lf_div",
+                reason: "not low power active",
+            });
         }
         Ok(clk.frequency)
     }
 
     pub fn ensure_fro_hf_div_active(&self, at_level: &PoweredClock) -> Result<u32, ClockError> {
         let Some(clk) = self.fro_hf_div.as_ref() else {
-            return Err(ClockError::BadConfig { clock: "fro_hf_div", reason: "required but not active" });
+            return Err(ClockError::BadConfig {
+                clock: "fro_hf_div",
+                reason: "required but not active",
+            });
         };
         if !clk.power.meets_requirement_of(at_level) {
-            return Err(ClockError::BadConfig { clock: "fro_hf_div", reason: "not low power active" });
+            return Err(ClockError::BadConfig {
+                clock: "fro_hf_div",
+                reason: "not low power active",
+            });
         }
         Ok(clk.frequency)
     }
@@ -657,10 +809,16 @@ impl Clocks {
 
     pub fn ensure_clk_1m_active(&self, at_level: &PoweredClock) -> Result<u32, ClockError> {
         let Some(clk) = self.clk_1m.as_ref() else {
-            return Err(ClockError::BadConfig { clock: "clk_1m", reason: "required but not active" });
+            return Err(ClockError::BadConfig {
+                clock: "clk_1m",
+                reason: "required but not active",
+            });
         };
         if !clk.power.meets_requirement_of(at_level) {
-            return Err(ClockError::BadConfig { clock: "clk_1m", reason: "not low power active" });
+            return Err(ClockError::BadConfig {
+                clock: "clk_1m",
+                reason: "not low power active",
+            });
         }
         Ok(clk.frequency)
     }
@@ -668,5 +826,4 @@ impl Clocks {
     pub fn ensure_pll1_clk_div_active(&self, _at_level: &PoweredClock) -> Result<u32, ClockError> {
         Err(ClockError::NotImplemented { clock: "pll1_clk_div" })
     }
-
 }
diff --git a/src/clocks/periph_helpers.rs b/src/clocks/periph_helpers.rs
index c4d4e9e3b..4d186acf8 100644
--- a/src/clocks/periph_helpers.rs
+++ b/src/clocks/periph_helpers.rs
@@ -7,6 +7,7 @@ pub trait SPConfHelper {
 
 // config types
 
+#[derive(Debug, Clone, Copy)]
 pub enum LpuartClockSel {
     /// FRO12M/FRO_LF/SIRC clock source, passed through divider
     /// "fro_lf_div"
@@ -45,7 +46,7 @@ pub struct LpuartConfig {
     pub div: Div8,
     /// Which instance is this?
     // NOTE: should not be user settable
-    instance: LpuartInstance,
+    pub(crate) instance: LpuartInstance,
 }
 
 // impls
diff --git a/src/lib.rs b/src/lib.rs
index 9899564d8..e3e603ef2 100644
--- a/src/lib.rs
+++ b/src/lib.rs
@@ -16,7 +16,19 @@ pub mod ostimer;
 pub mod rtc;
 pub mod uart;
 
-embassy_hal_internal::peripherals!(LPUART2, OSTIMER0, GPIO, RTC0, ADC1,);
+embassy_hal_internal::peripherals!(
+    PORT1,
+    PORT2,
+    PORT3,
+    LPUART2,
+    OSTIMER0,
+    GPIO,
+    PIO2_2,
+    PIO2_3,
+    GPIO3,
+    RTC0,
+    ADC1,
+);
 
 /// Get access to the PAC Peripherals for low-level register access.
 /// This is a lazy-initialized singleton that can be called after init().
diff --git a/src/lpuart/buffered.rs b/src/lpuart/buffered.rs
index a617c10a5..7b575c086 100644
--- a/src/lpuart/buffered.rs
+++ b/src/lpuart/buffered.rs
@@ -212,10 +212,19 @@ impl<'a> BufferedLpuart<'a> {
         config.enable_tx = true;
         config.enable_rx = true;
 
+        // Enable clocks
+        let conf = LpuartConfig {
+            power: config.power,
+            source: config.source,
+            div: config.div,
+            instance: T::CLOCK_INSTANCE,
+        };
+        let clock_freq = unsafe { enable_and_reset::<T>(&conf).map_err(Error::ClockSetup)? };
+
         // Perform standard initialization
         perform_software_reset(regs);
         disable_transceiver(regs);
-        configure_baudrate(regs, config.baudrate_bps, config.clock)?;
+        configure_baudrate(regs, config.baudrate_bps, clock_freq)?;
         configure_frame_format(regs, &config);
         configure_control_settings(regs, &config);
         configure_fifo(regs, &config);
diff --git a/src/lpuart/mod.rs b/src/lpuart/mod.rs
index 35b531421..41ec951ec 100644
--- a/src/lpuart/mod.rs
+++ b/src/lpuart/mod.rs
@@ -3,6 +3,8 @@ use core::marker::PhantomData;
 use embassy_hal_internal::{Peri, PeripheralType};
 use paste::paste;
 
+use crate::clocks::periph_helpers::{LpuartClockSel, LpuartConfig};
+use crate::clocks::{enable_and_reset, ClockError, Div8, Gate, PoweredClock};
 use crate::pac::lpuart0::baud::Sbns as StopBits;
 use crate::pac::lpuart0::ctrl::{Idlecfg as IdleConfig, Ilt as IdleType, Pt as Parity, M as DataBits};
 use crate::pac::lpuart0::modir::{Txctsc as TxCtsConfig, Txctssrc as TxCtsSource};
@@ -18,70 +20,7 @@ pub mod buffered;
 // Stub implementation for LIB (Peripherals), GPIO, DMA and CLOCK until stable API
 // Pin and Clock initialization is currently done at the examples level.
 
-// --- START LIB ---
-
-// Use our own instance of Peripherals, until we align `lib.rs` with the EMBASSY-IMXRT approach
-// Inlined peripherals_definition! to bypass the `Peripherals::take_with_cs()` check
-// SHOULD NOT BE USED IN THE FINAL VERSION
-pub mod lib {
-    // embassy_hal_internal::peripherals!(LPUART2, PIO2_2, PIO2_3)
-
-    embassy_hal_internal::peripherals_definition!(LPUART2, PIO2_2, PIO2_3,);
-    #[doc = r" Struct containing all the peripheral singletons."]
-    #[doc = r""]
-    #[doc = r" To obtain the peripherals, you must initialize the HAL, by calling [`crate::init`]."]
-    #[allow(non_snake_case)]
-    pub struct Peripherals {
-        #[doc = concat!(stringify!(LPUART2)," peripheral")]
-        pub LPUART2: embassy_hal_internal::Peri<'static, peripherals::LPUART2>,
-        #[doc = concat!(stringify!(PIO2_2)," peripheral")]
-        pub PIO2_2: embassy_hal_internal::Peri<'static, peripherals::PIO2_2>,
-        #[doc = concat!(stringify!(PIO2_3)," peripheral")]
-        pub PIO2_3: embassy_hal_internal::Peri<'static, peripherals::PIO2_3>,
-    }
-    impl Peripherals {
-        #[doc = r"Returns all the peripherals *once*"]
-        #[inline]
-        pub(crate) fn take() -> Self {
-            critical_section::with(Self::take_with_cs)
-        }
-        #[doc = r"Returns all the peripherals *once*"]
-        #[inline]
-        pub(crate) fn take_with_cs(_cs: critical_section::CriticalSection) -> Self {
-            #[no_mangle]
-            static mut _EMBASSY_DEVICE_PERIPHERALS2: bool = false; // ALIGN: Temporary fix to use stub Peripherals
-            unsafe {
-                if _EMBASSY_DEVICE_PERIPHERALS2 {
-                    panic!("init called more than once!")
-                }
-                _EMBASSY_DEVICE_PERIPHERALS2 = true;
-                Self::steal()
-            }
-        }
-    }
-    impl Peripherals {
-        #[doc = r" Unsafely create an instance of this peripheral out of thin air."]
-        #[doc = r""]
-        #[doc = r" # Safety"]
-        #[doc = r""]
-        #[doc = r" You must ensure that you're only using one instance of this type at a time."]
-        #[inline]
-        pub unsafe fn steal() -> Self {
-            Self {
-                LPUART2: peripherals::LPUART2::steal(),
-                PIO2_2: peripherals::PIO2_2::steal(),
-                PIO2_3: peripherals::PIO2_3::steal(),
-            }
-        }
-    }
-
-    /// Initialize HAL
-    pub fn init() -> Peripherals {
-        Peripherals::take()
-    }
-}
 
-// --- END LIB ---
 
 // --- START GPIO ---
 
@@ -101,13 +40,13 @@ mod gpio {
     macro_rules! impl_gpio_pin {
         ($($pin:ident),*) => {
             $(
-                impl SealedPin for super::lib::peripherals::$pin {}
+                impl SealedPin for crate::peripherals::$pin {}
 
-                impl GpioPin for super::lib::peripherals::$pin {}
+                impl GpioPin for crate::peripherals::$pin {}
 
-                impl From<super::lib::peripherals::$pin> for AnyPin {
+                impl From<crate::peripherals::$pin> for AnyPin {
                     // TODO: AJM: any reason we aren't using $pin?
-                    fn from(_val: super::lib::peripherals::$pin) -> Self {
+                    fn from(_val: crate::peripherals::$pin) -> Self {
                         AnyPin
                     }
                 }
@@ -143,18 +82,6 @@ use dma::Channel;
 
 // --- END DMA ---
 
-// --- START CLOCK ---
-mod clock {
-    #[derive(Debug, Clone, Copy)]
-    pub enum Clock {
-        FroLf, // Low-Frequency Free-Running Oscillator
-    }
-}
-
-use clock::Clock;
-
-// --- END CLOCK ---
-
 // ============================================================================
 // MISC
 // ============================================================================
@@ -182,7 +109,8 @@ pub struct Info {
 
 /// Trait for LPUART peripheral instances
 #[allow(private_bounds)]
-pub trait Instance: SealedInstance + PeripheralType + 'static + Send {
+pub trait Instance: SealedInstance + PeripheralType + 'static + Send + Gate<MrccPeriphConfig = LpuartConfig> {
+    const CLOCK_INSTANCE: crate::clocks::periph_helpers::LpuartInstance;
     type Interrupt: interrupt::typelevel::Interrupt;
 }
 
@@ -190,7 +118,7 @@ macro_rules! impl_instance {
     ($($n:expr),*) => {
         $(
             paste!{
-                impl SealedInstance for lib::peripherals::[<LPUART $n>] {
+                impl SealedInstance for crate::peripherals::[<LPUART $n>] {
                     fn info() -> Info {
                         Info {
                             regs: unsafe { &*pac::[<Lpuart $n>]::ptr() },
@@ -208,7 +136,9 @@ macro_rules! impl_instance {
                     }
                 }
 
-                impl Instance for lib::peripherals::[<LPUART $n>] {
+                impl Instance for crate::peripherals::[<LPUART $n>] {
+                    const CLOCK_INSTANCE: crate::clocks::periph_helpers::LpuartInstance
+                        = crate::clocks::periph_helpers::LpuartInstance::[<Lpuart $n>];
                     type Interrupt = crate::interrupt::typelevel::[<LPUART $n>];
                 }
             }
@@ -236,8 +166,7 @@ pub fn disable_transceiver(regs: Regs) {
 }
 
 /// Calculate and configure baudrate settings
-pub fn configure_baudrate(regs: Regs, baudrate_bps: u32, clock: Clock) -> Result<()> {
-    let clock_freq = get_fc_freq(clock)?;
+pub fn configure_baudrate(regs: Regs, baudrate_bps: u32, clock_freq: u32) -> Result<()> {
     let (osr, sbr) = calculate_baudrate(baudrate_bps, clock_freq)?;
 
     // Configure BAUD register
@@ -408,16 +337,6 @@ pub fn calculate_baudrate(baudrate: u32, src_clock_hz: u32) -> Result<(u8, u16)>
     Ok((osr, sbr))
 }
 
-pub fn get_fc_freq(clock: Clock) -> Result<u32> {
-    // This is a placeholder - actual implementation would query the clock system
-    // In real implementation, this would get the LPUART clock frequency
-    match clock {
-        Clock::FroLf => Ok(12_000_000), // Low frequency oscillator
-        #[allow(unreachable_patterns)]
-        _ => Err(Error::InvalidArgument),
-    }
-}
-
 /// Wait for all transmit operations to complete
 pub fn wait_for_tx_complete(regs: Regs) {
     // Wait for TX FIFO to empty
@@ -504,7 +423,7 @@ macro_rules! impl_pin_trait {
     ($fcn:ident, $mode:ident, $($pin:ident, $alt:ident),*) => {
         paste! {
             $(
-                impl [<$mode:camel Pin>]<lib::peripherals::$fcn> for lib::peripherals::$pin {
+                impl [<$mode:camel Pin>]<crate::peripherals::$fcn> for crate::peripherals::$pin {
                     fn [<as_ $mode>](&self) {
                         let _alt = gpio::Alt::$alt;
                         // todo!("Configure pin for LPUART function")
@@ -553,6 +472,8 @@ pub enum Error {
     TxFifoFull,
     /// TX Busy
     TxBusy,
+    /// Clock Error
+    ClockSetup(ClockError),
 }
 
 /// A specialized Result type for LPUART operations
@@ -565,10 +486,14 @@ pub type Result<T> = core::result::Result<T, Error>;
 /// Lpuart config
 #[derive(Debug, Clone, Copy)]
 pub struct Config {
+    /// Power state required for this peripheral
+    pub power: PoweredClock,
+    /// Clock source
+    pub source: LpuartClockSel,
+    /// Clock divisor
+    pub div: Div8,
     /// Baud rate in bits per second
     pub baudrate_bps: u32,
-    /// Clock
-    pub clock: Clock,
     /// Parity configuration
     pub parity_mode: Option<Parity>,
     /// Number of data bits
@@ -605,7 +530,6 @@ impl Default for Config {
     fn default() -> Self {
         Self {
             baudrate_bps: 115_200u32,
-            clock: Clock::FroLf,
             parity_mode: None,
             data_bits_count: DataBits::Data8,
             msb_firs: MsbFirst::LsbFirst,
@@ -621,6 +545,9 @@ impl Default for Config {
             enable_tx: false,
             enable_rx: false,
             swap_txd_rxd: false,
+            power: PoweredClock::NormalEnabledDeepSleepDisabled,
+            source: LpuartClockSel::FroLfDiv,
+            div: const { Div8::from_divisor(1).unwrap() },
         }
     }
 }
@@ -706,10 +633,21 @@ impl<'a, M: Mode> Lpuart<'a, M> {
     ) -> Result<()> {
         let regs = T::info().regs;
 
+        // Enable clocks
+        let conf = LpuartConfig {
+            power: config.power,
+            source: config.source,
+            div: config.div,
+            instance: T::CLOCK_INSTANCE,
+        };
+        let clock_freq = unsafe {
+            enable_and_reset::<T>(&conf).map_err(Error::ClockSetup)?
+        };
+
         // Perform initialization sequence
         perform_software_reset(regs);
         disable_transceiver(regs);
-        configure_baudrate(regs, config.baudrate_bps, config.clock)?;
+        configure_baudrate(regs, config.baudrate_bps, clock_freq)?;
         configure_frame_format(regs, &config);
         configure_control_settings(regs, &config);
         configure_fifo(regs, &config);