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authorDario Nieuwenhuis <[email protected]>2022-08-25 15:52:10 +0200
committerGitHub <[email protected]>2022-08-25 15:52:10 +0200
commit69e92e5639e0a86994c9bdf647a0f2d57f768898 (patch)
treeacbfc66b427f5a57c9d24fa0e45ea48a5b7766c4 /src
parent193124bed171eb5dcf4a98502dd760e4faccdffa (diff)
parentf2ac14b86f21c31221bba1e1653e2a9020d60d8e (diff)
Merge pull request #6 from danbev/add-word-length-constants
Add WORD_LENGTH_32 constant
Diffstat (limited to 'src')
-rw-r--r--src/lib.rs6
1 files changed, 4 insertions, 2 deletions
diff --git a/src/lib.rs b/src/lib.rs
index fe4d10ba2..8f439cf2f 100644
--- a/src/lib.rs
+++ b/src/lib.rs
@@ -53,6 +53,8 @@ const REG_BUS_STATUS: u32 = 0x8;
53const REG_BUS_TEST_RO: u32 = 0x14; 53const REG_BUS_TEST_RO: u32 = 0x14;
54const REG_BUS_TEST_RW: u32 = 0x18; 54const REG_BUS_TEST_RW: u32 = 0x18;
55const REG_BUS_RESP_DELAY: u32 = 0x1c; 55const REG_BUS_RESP_DELAY: u32 = 0x1c;
56const WORD_LENGTH_32: u32 = 0x1;
57const HIGH_SPEED: u32 = 0x10;
56 58
57// SPI_STATUS_REGISTER bits 59// SPI_STATUS_REGISTER bits
58const STATUS_DATA_NOT_AVAILABLE: u32 = 0x00000001; 60const STATUS_DATA_NOT_AVAILABLE: u32 = 0x00000001;
@@ -572,8 +574,8 @@ where
572 let val = self.read32_swapped(REG_BUS_TEST_RW).await; 574 let val = self.read32_swapped(REG_BUS_TEST_RW).await;
573 assert_eq!(val, TEST_PATTERN); 575 assert_eq!(val, TEST_PATTERN);
574 576
575 // 32bit, little endian. 577 // 32-bit word length, little endian (which is the default endianess).
576 self.write32_swapped(REG_BUS_CTRL, 0x00010031).await; 578 self.write32_swapped(REG_BUS_CTRL, WORD_LENGTH_32 | HIGH_SPEED).await;
577 579
578 let val = self.read32(FUNC_BUS, REG_BUS_TEST_RO).await; 580 let val = self.read32(FUNC_BUS, REG_BUS_TEST_RO).await;
579 assert_eq!(val, FEEDBEAD); 581 assert_eq!(val, FEEDBEAD);