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authorkalkyl <[email protected]>2023-05-13 06:34:03 +0200
committerkalkyl <[email protected]>2023-05-13 06:34:03 +0200
commit6c1137177f92f9a5c5cd9c2a0450b5db5165f8be (patch)
tree57e4ff4a4d4e15c2fddd7242c17c131ec3ba859c /src
parentbbd687fcb0e63a1bb8eb4d31c8f5ed2f403603f6 (diff)
Wait until there's enough space in tx buffer, remove busy wait for completed send
Diffstat (limited to 'src')
-rw-r--r--src/device.rs25
-rw-r--r--src/socket.rs11
2 files changed, 4 insertions, 32 deletions
diff --git a/src/device.rs b/src/device.rs
index 3875fde0e..8158bc98e 100644
--- a/src/device.rs
+++ b/src/device.rs
@@ -123,31 +123,14 @@ impl<SPI: SpiDevice> W5500<SPI> {
123 123
124 /// Write an ethernet frame to the device. Returns number of bytes written 124 /// Write an ethernet frame to the device. Returns number of bytes written
125 pub async fn write_frame(&mut self, frame: &[u8]) -> Result<usize, SPI::Error> { 125 pub async fn write_frame(&mut self, frame: &[u8]) -> Result<usize, SPI::Error> {
126 let max_size = socket::get_tx_free_size(&mut self.bus).await? as usize; 126 while socket::get_tx_free_size(&mut self.bus).await? < frame.len() as u16 {}
127
128 let write_data = if frame.len() < max_size {
129 frame
130 } else {
131 &frame[..max_size]
132 };
133
134 let write_ptr = socket::get_tx_write_ptr(&mut self.bus).await?; 127 let write_ptr = socket::get_tx_write_ptr(&mut self.bus).await?;
135 self.bus 128 self.bus
136 .write_frame(RegisterBlock::TxBuf, write_ptr, write_data) 129 .write_frame(RegisterBlock::TxBuf, write_ptr, frame)
137 .await?; 130 .await?;
138 socket::set_tx_write_ptr( 131 socket::set_tx_write_ptr(&mut self.bus, write_ptr.wrapping_add(frame.len() as u16)).await?;
139 &mut self.bus,
140 write_ptr.wrapping_add(write_data.len() as u16),
141 )
142 .await?;
143
144 socket::reset_interrupt(&mut self.bus, socket::Interrupt::SendOk).await?;
145 socket::command(&mut self.bus, socket::Command::Send).await?; 132 socket::command(&mut self.bus, socket::Command::Send).await?;
146 // Wait for TX to complete 133 Ok(frame.len())
147 while !socket::is_interrupt(&mut self.bus, socket::Interrupt::SendOk).await? {}
148 socket::reset_interrupt(&mut self.bus, socket::Interrupt::SendOk).await?;
149
150 Ok(write_data.len())
151 } 134 }
152 135
153 pub async fn is_link_up(&mut self) -> bool { 136 pub async fn is_link_up(&mut self) -> bool {
diff --git a/src/socket.rs b/src/socket.rs
index 0d3d1aeb2..3f64d04d1 100644
--- a/src/socket.rs
+++ b/src/socket.rs
@@ -22,7 +22,6 @@ pub enum Command {
22pub const INTR: u16 = 0x02; 22pub const INTR: u16 = 0x02;
23#[repr(u8)] 23#[repr(u8)]
24pub enum Interrupt { 24pub enum Interrupt {
25 SendOk = 0b010000_u8,
26 Receive = 0b00100_u8, 25 Receive = 0b00100_u8,
27} 26}
28 27
@@ -34,16 +33,6 @@ pub async fn reset_interrupt<SPI: SpiDevice>(
34 bus.write_frame(RegisterBlock::Socket0, INTR, &data).await 33 bus.write_frame(RegisterBlock::Socket0, INTR, &data).await
35} 34}
36 35
37pub async fn is_interrupt<SPI: SpiDevice>(
38 bus: &mut SpiInterface<SPI>,
39 code: Interrupt,
40) -> Result<bool, SPI::Error> {
41 let mut data = [0u8];
42 bus.read_frame(RegisterBlock::Socket0, INTR, &mut data)
43 .await?;
44 Ok(data[0] & code as u8 != 0)
45}
46
47pub async fn get_tx_write_ptr<SPI: SpiDevice>( 36pub async fn get_tx_write_ptr<SPI: SpiDevice>(
48 bus: &mut SpiInterface<SPI>, 37 bus: &mut SpiInterface<SPI>,
49) -> Result<u16, SPI::Error> { 38) -> Result<u16, SPI::Error> {