:rainbow:

4 files changed, 426 insertions, 0 deletions

diff --git a/src/device.rs b/src/device.rs
new file mode 100644
index 000000000..3875fde0e
--- /dev/null
+++ b/src/device.rs
@@ -0,0 +1,161 @@
+use crate::socket;
+use crate::spi::SpiInterface;
+use embedded_hal_async::spi::SpiDevice;
+
+pub const MODE: u16 = 0x00;
+pub const MAC: u16 = 0x09;
+pub const SOCKET_INTR: u16 = 0x18;
+pub const PHY_CFG: u16 = 0x2E;
+
+#[repr(u8)]
+pub enum RegisterBlock {
+    Common = 0x00,
+    Socket0 = 0x01,
+    TxBuf = 0x02,
+    RxBuf = 0x03,
+}
+
+/// W5500 in MACRAW mode
+#[derive(Debug)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub struct W5500<SPI> {
+    bus: SpiInterface<SPI>,
+}
+
+impl<SPI: SpiDevice> W5500<SPI> {
+    /// Create and initialize the W5500 driver
+    pub async fn new(spi: SPI, mac_addr: [u8; 6]) -> Result<W5500<SPI>, SPI::Error> {
+        let mut bus = SpiInterface(spi);
+        // Reset device
+        bus.write_frame(RegisterBlock::Common, MODE, &[0x80])
+            .await?;
+
+        // Enable interrupt pin
+        bus.write_frame(RegisterBlock::Common, SOCKET_INTR, &[0x01])
+            .await?;
+        // Enable receive interrupt
+        bus.write_frame(
+            RegisterBlock::Socket0,
+            socket::SOCKET_INTR_MASK,
+            &[socket::Interrupt::Receive as u8],
+        )
+        .await?;
+
+        // Set MAC address
+        bus.write_frame(RegisterBlock::Common, MAC, &mac_addr)
+            .await?;
+
+        // Set the raw socket RX/TX buffer sizes to  16KB
+        bus.write_frame(RegisterBlock::Socket0, socket::TXBUF_SIZE, &[16])
+            .await?;
+        bus.write_frame(RegisterBlock::Socket0, socket::RXBUF_SIZE, &[16])
+            .await?;
+
+        // MACRAW mode with MAC filtering.
+        let mode: u8 = (1 << 2) | (1 << 7);
+        bus.write_frame(RegisterBlock::Socket0, socket::MODE, &[mode])
+            .await?;
+        socket::command(&mut bus, socket::Command::Open).await?;
+
+        Ok(Self { bus })
+    }
+
+    /// Read bytes from the RX buffer. Returns the number of bytes read.
+    async fn read_bytes(&mut self, buffer: &mut [u8], offset: u16) -> Result<usize, SPI::Error> {
+        let rx_size = socket::get_rx_size(&mut self.bus).await? as usize;
+
+        let read_buffer = if rx_size > buffer.len() + offset as usize {
+            buffer
+        } else {
+            &mut buffer[..rx_size - offset as usize]
+        };
+
+        let read_ptr = socket::get_rx_read_ptr(&mut self.bus)
+            .await?
+            .wrapping_add(offset);
+        self.bus
+            .read_frame(RegisterBlock::RxBuf, read_ptr, read_buffer)
+            .await?;
+        socket::set_rx_read_ptr(
+            &mut self.bus,
+            read_ptr.wrapping_add(read_buffer.len() as u16),
+        )
+        .await?;
+
+        Ok(read_buffer.len())
+    }
+
+    /// Read an ethernet frame from the device. Returns the number of bytes read.
+    pub async fn read_frame(&mut self, frame: &mut [u8]) -> Result<usize, SPI::Error> {
+        let rx_size = socket::get_rx_size(&mut self.bus).await? as usize;
+        if rx_size == 0 {
+            return Ok(0);
+        }
+
+        socket::reset_interrupt(&mut self.bus, socket::Interrupt::Receive).await?;
+
+        // First two bytes gives the size of the received ethernet frame
+        let expected_frame_size: usize = {
+            let mut frame_bytes = [0u8; 2];
+            assert!(self.read_bytes(&mut frame_bytes[..], 0).await? == 2);
+            u16::from_be_bytes(frame_bytes) as usize - 2
+        };
+
+        // Read the ethernet frame
+        let read_buffer = if frame.len() > expected_frame_size {
+            &mut frame[..expected_frame_size]
+        } else {
+            frame
+        };
+
+        let recvd_frame_size = self.read_bytes(read_buffer, 2).await?;
+
+        // Register RX as completed
+        socket::command(&mut self.bus, socket::Command::Receive).await?;
+
+        // If the whole frame wasn't read, drop it
+        if recvd_frame_size < expected_frame_size {
+            Ok(0)
+        } else {
+            Ok(recvd_frame_size)
+        }
+    }
+
+    /// Write an ethernet frame to the device. Returns number of bytes written
+    pub async fn write_frame(&mut self, frame: &[u8]) -> Result<usize, SPI::Error> {
+        let max_size = socket::get_tx_free_size(&mut self.bus).await? as usize;
+
+        let write_data = if frame.len() < max_size {
+            frame
+        } else {
+            &frame[..max_size]
+        };
+
+        let write_ptr = socket::get_tx_write_ptr(&mut self.bus).await?;
+        self.bus
+            .write_frame(RegisterBlock::TxBuf, write_ptr, write_data)
+            .await?;
+        socket::set_tx_write_ptr(
+            &mut self.bus,
+            write_ptr.wrapping_add(write_data.len() as u16),
+        )
+        .await?;
+
+        socket::reset_interrupt(&mut self.bus, socket::Interrupt::SendOk).await?;
+        socket::command(&mut self.bus, socket::Command::Send).await?;
+        // Wait for TX to complete
+        while !socket::is_interrupt(&mut self.bus, socket::Interrupt::SendOk).await? {}
+        socket::reset_interrupt(&mut self.bus, socket::Interrupt::SendOk).await?;
+
+        Ok(write_data.len())
+    }
+
+    pub async fn is_link_up(&mut self) -> bool {
+        let mut link = [0];
+        self.bus
+            .read_frame(RegisterBlock::Common, PHY_CFG, &mut link)
+            .await
+            .ok();
+        link[0] & 1 == 1
+    }
+}
diff --git a/src/lib.rs b/src/lib.rs
new file mode 100644
index 000000000..bf14b05b4
--- /dev/null
+++ b/src/lib.rs
@@ -0,0 +1,114 @@
+#![no_std]
+/// [`embassy-net`](crates.io/crates/embassy-net) driver for the WIZnet W5500 ethernet chip.
+mod device;
+mod socket;
+mod spi;
+
+use crate::device::W5500;
+use embassy_futures::select::{select, Either};
+use embassy_net_driver_channel as ch;
+use embassy_net_driver_channel::driver::LinkState;
+use embassy_time::{Duration, Timer};
+use embedded_hal::digital::OutputPin;
+use embedded_hal_async::digital::Wait;
+use embedded_hal_async::spi::SpiDevice;
+const MTU: usize = 1514;
+
+/// Type alias for the embassy-net driver for W5500
+pub type Device<'d> = embassy_net_driver_channel::Device<'d, MTU>;
+
+/// Internal state for the embassy-net integration.
+pub struct State<const N_RX: usize, const N_TX: usize> {
+    ch_state: ch::State<MTU, N_RX, N_TX>,
+}
+
+impl<const N_RX: usize, const N_TX: usize> State<N_RX, N_TX> {
+    /// Create a new `State`.
+    pub const fn new() -> Self {
+        Self {
+            ch_state: ch::State::new(),
+        }
+    }
+}
+
+/// Background runner for the W5500.
+///
+/// You must call `.run()` in a background task for the W5500 to operate.
+pub struct Runner<'d, SPI: SpiDevice, INT: Wait, RST: OutputPin> {
+    mac: W5500<SPI>,
+    ch: ch::Runner<'d, MTU>,
+    int: INT,
+    _reset: RST,
+}
+
+/// You must call this in a background task for the W5500 to operate.
+impl<'d, SPI: SpiDevice, INT: Wait, RST: OutputPin> Runner<'d, SPI, INT, RST> {
+    pub async fn run(mut self) -> ! {
+        let (state_chan, mut rx_chan, mut tx_chan) = self.ch.split();
+        loop {
+            if self.mac.is_link_up().await {
+                state_chan.set_link_state(LinkState::Up);
+                loop {
+                    match select(
+                        async {
+                            self.int.wait_for_low().await.ok();
+                            rx_chan.rx_buf().await
+                        },
+                        tx_chan.tx_buf(),
+                    )
+                    .await
+                    {
+                        Either::First(p) => {
+                            if let Ok(n) = self.mac.read_frame(p).await {
+                                rx_chan.rx_done(n);
+                            }
+                        }
+                        Either::Second(p) => {
+                            self.mac.write_frame(p).await.ok();
+                            tx_chan.tx_done();
+                        }
+                    }
+                }
+            } else {
+                state_chan.set_link_state(LinkState::Down);
+            }
+        }
+    }
+}
+
+/// Obtain a driver for using the W5500 with [`embassy-net`](crates.io/crates/embassy-net).
+pub async fn new<
+    'a,
+    const N_RX: usize,
+    const N_TX: usize,
+    SPI: SpiDevice,
+    INT: Wait,
+    RST: OutputPin,
+>(
+    mac_addr: [u8; 6],
+    state: &'a mut State<N_RX, N_TX>,
+    spi_dev: SPI,
+    int: INT,
+    mut reset: RST,
+) -> (Device<'a>, Runner<'a, SPI, INT, RST>) {
+    // Reset the W5500.
+    reset.set_low().ok();
+    // Ensure the reset is registered.
+    Timer::after(Duration::from_millis(1)).await;
+    reset.set_high().ok();
+    // Wait for the W5500 to achieve PLL lock.
+    Timer::after(Duration::from_millis(2)).await;
+
+    let mac = W5500::new(spi_dev, mac_addr).await.unwrap();
+
+    let (runner, device) = ch::new(&mut state.ch_state, mac_addr);
+    (
+        device,
+        Runner {
+            ch: runner,
+            mac,
+            int,
+            _reset: reset,
+        },
+    )
+}
diff --git a/src/socket.rs b/src/socket.rs
new file mode 100644
index 000000000..0d3d1aeb2
--- /dev/null
+++ b/src/socket.rs
@@ -0,0 +1,114 @@
+use crate::device::RegisterBlock;
+use crate::spi::SpiInterface;
+use embedded_hal_async::spi::SpiDevice;
+
+pub const MODE: u16 = 0x00;
+pub const COMMAND: u16 = 0x01;
+pub const RXBUF_SIZE: u16 = 0x1E;
+pub const TXBUF_SIZE: u16 = 0x1F;
+pub const TX_FREE_SIZE: u16 = 0x20;
+pub const TX_DATA_WRITE_PTR: u16 = 0x24;
+pub const RECVD_SIZE: u16 = 0x26;
+pub const RX_DATA_READ_PTR: u16 = 0x28;
+pub const SOCKET_INTR_MASK: u16 = 0x2C;
+
+#[repr(u8)]
+pub enum Command {
+    Open = 0x01,
+    Send = 0x20,
+    Receive = 0x40,
+}
+
+pub const INTR: u16 = 0x02;
+#[repr(u8)]
+pub enum Interrupt {
+    SendOk = 0b010000_u8,
+    Receive = 0b00100_u8,
+}
+
+pub async fn reset_interrupt<SPI: SpiDevice>(
+    bus: &mut SpiInterface<SPI>,
+    code: Interrupt,
+) -> Result<(), SPI::Error> {
+    let data = [code as u8];
+    bus.write_frame(RegisterBlock::Socket0, INTR, &data).await
+}
+
+pub async fn is_interrupt<SPI: SpiDevice>(
+    bus: &mut SpiInterface<SPI>,
+    code: Interrupt,
+) -> Result<bool, SPI::Error> {
+    let mut data = [0u8];
+    bus.read_frame(RegisterBlock::Socket0, INTR, &mut data)
+        .await?;
+    Ok(data[0] & code as u8 != 0)
+}
+
+pub async fn get_tx_write_ptr<SPI: SpiDevice>(
+    bus: &mut SpiInterface<SPI>,
+) -> Result<u16, SPI::Error> {
+    let mut data = [0u8; 2];
+    bus.read_frame(RegisterBlock::Socket0, TX_DATA_WRITE_PTR, &mut data)
+        .await?;
+    Ok(u16::from_be_bytes(data))
+}
+
+pub async fn set_tx_write_ptr<SPI: SpiDevice>(
+    bus: &mut SpiInterface<SPI>,
+    ptr: u16,
+) -> Result<(), SPI::Error> {
+    let data = ptr.to_be_bytes();
+    bus.write_frame(RegisterBlock::Socket0, TX_DATA_WRITE_PTR, &data)
+        .await
+}
+
+pub async fn get_rx_read_ptr<SPI: SpiDevice>(
+    bus: &mut SpiInterface<SPI>,
+) -> Result<u16, SPI::Error> {
+    let mut data = [0u8; 2];
+    bus.read_frame(RegisterBlock::Socket0, RX_DATA_READ_PTR, &mut data)
+        .await?;
+    Ok(u16::from_be_bytes(data))
+}
+
+pub async fn set_rx_read_ptr<SPI: SpiDevice>(
+    bus: &mut SpiInterface<SPI>,
+    ptr: u16,
+) -> Result<(), SPI::Error> {
+    let data = ptr.to_be_bytes();
+    bus.write_frame(RegisterBlock::Socket0, RX_DATA_READ_PTR, &data)
+        .await
+}
+
+pub async fn command<SPI: SpiDevice>(
+    bus: &mut SpiInterface<SPI>,
+    command: Command,
+) -> Result<(), SPI::Error> {
+    let data = [command as u8];
+    bus.write_frame(RegisterBlock::Socket0, COMMAND, &data)
+        .await
+}
+
+pub async fn get_rx_size<SPI: SpiDevice>(bus: &mut SpiInterface<SPI>) -> Result<u16, SPI::Error> {
+    loop {
+        // Wait until two sequential reads are equal
+        let mut res0 = [0u8; 2];
+        bus.read_frame(RegisterBlock::Socket0, RECVD_SIZE, &mut res0)
+            .await?;
+        let mut res1 = [0u8; 2];
+        bus.read_frame(RegisterBlock::Socket0, RECVD_SIZE, &mut res1)
+            .await?;
+        if res0 == res1 {
+            break Ok(u16::from_be_bytes(res0));
+        }
+    }
+}
+
+pub async fn get_tx_free_size<SPI: SpiDevice>(
+    bus: &mut SpiInterface<SPI>,
+) -> Result<u16, SPI::Error> {
+    let mut data = [0; 2];
+    bus.read_frame(RegisterBlock::Socket0, TX_FREE_SIZE, &mut data)
+        .await?;
+    Ok(u16::from_be_bytes(data))
+}
diff --git a/src/spi.rs b/src/spi.rs
new file mode 100644
index 000000000..55d311888
--- /dev/null
+++ b/src/spi.rs
@@ -0,0 +1,37 @@
+use crate::device::RegisterBlock;
+use embedded_hal_async::spi::{Operation, SpiDevice};
+
+#[derive(Debug)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub struct SpiInterface<SPI>(pub SPI);
+
+impl<SPI: SpiDevice> SpiInterface<SPI> {
+    pub async fn read_frame(
+        &mut self,
+        block: RegisterBlock,
+        address: u16,
+        data: &mut [u8],
+    ) -> Result<(), SPI::Error> {
+        let address_phase = address.to_be_bytes();
+        let control_phase = [(block as u8) << 3];
+        let operations = &mut [
+            Operation::Write(&address_phase),
+            Operation::Write(&control_phase),
+            Operation::TransferInPlace(data),
+        ];
+        self.0.transaction(operations).await
+    }
+
+    pub async fn write_frame(
+        &mut self,
+        block: RegisterBlock,
+        address: u16,
+        data: &[u8],
+    ) -> Result<(), SPI::Error> {
+        let address_phase = address.to_be_bytes();
+        let control_phase = [(block as u8) << 3 | 0b0000_0100];
+        let data_phase = data;
+        let operations = &[&address_phase[..], &control_phase, &data_phase];
+        self.0.write_transaction(operations).await
+    }
+}