Merge pull request #13 from jamesmunns/james/repac

Switch to new PAC commit

8 files changed, 67 insertions, 31 deletions

diff --git a/src/adc.rs b/src/adc.rs
index d456971f7..655bf934f 100644
--- a/src/adc.rs
+++ b/src/adc.rs
@@ -228,7 +228,7 @@ impl<I: Instance> Adc<I> {
             let step = 1.0 / (1u32 << shift) as f32;
             let tmp = (gain_adjustment / step) as u32;
             gcra_array[i - 1] = tmp;
-            gain_adjustment = gain_adjustment - tmp as f32 * step;
+            gain_adjustment -= tmp as f32 * step;
         }
 
         for i in (1..=17).rev() {
@@ -244,7 +244,7 @@ impl<I: Instance> Adc<I> {
         while adc.gcc0().read().rdy().is_gain_cal_not_valid() {}
 
         let mut gcca = adc.gcc0().read().gain_cal().bits() as u32;
-        if gcca & (((0xFFFF >> 0) + 1) >> 1) != 0 {
+        if gcca & ((0xFFFF + 1) >> 1) != 0 {
             gcca |= !0xFFFF;
         }
 
diff --git a/src/interrupt.rs b/src/interrupt.rs
index 09d7acbef..134ff03fd 100644
--- a/src/interrupt.rs
+++ b/src/interrupt.rs
@@ -2,6 +2,10 @@
 //! Type-level interrupt traits and bindings are provided by the
 //! `embassy_hal_internal::interrupt_mod!` macro via the generated module below.
 
+// TODO(AJM): As of 2025-11-13, we need to do a pass to ensure safety docs
+// are complete prior to release.
+#![allow(clippy::missing_safety_doc)]
+
 mod generated {
     embassy_hal_internal::interrupt_mod!(OS_EVENT, LPUART2, RTC, ADC1);
 }
diff --git a/src/lib.rs b/src/lib.rs
index fe27aadba..9899564d8 100644
--- a/src/lib.rs
+++ b/src/lib.rs
@@ -1,4 +1,7 @@
 #![no_std]
+// TODO(AJM): As of 2025-11-13, we need to do a pass to ensure safety docs
+// are complete prior to release.
+#![allow(clippy::missing_safety_doc)]
 
 pub mod clocks; // still provide clock helpers
 pub mod gpio;
diff --git a/src/lpuart/buffered.rs b/src/lpuart/buffered.rs
index 0413fed8e..a617c10a5 100644
--- a/src/lpuart/buffered.rs
+++ b/src/lpuart/buffered.rs
@@ -24,6 +24,12 @@ pub struct State {
     initialized: AtomicBool,
 }
 
+impl Default for State {
+    fn default() -> Self {
+        Self::new()
+    }
+}
+
 impl State {
     /// Create a new state instance
     pub const fn new() -> Self {
@@ -104,6 +110,7 @@ impl<'a> BufferedLpuart<'a> {
     }
 
     /// Create a new buffered LPUART with flexible pin configuration
+    #[allow(clippy::too_many_arguments)]
     pub fn new_with_pins<T: Instance>(
         _inner: Peri<'a, T>,
         tx_pin: Option<Peri<'a, impl TxPin<T>>>,
@@ -612,16 +619,14 @@ impl<T: Instance> crate::interrupt::typelevel::Handler<T::Interrupt> for Buffere
         }
 
         // Handle transmission complete
-        if ctrl.tcie().is_enabled() {
-            if regs.stat().read().tc().is_complete() {
-                state.tx_done.store(true, Ordering::Release);
-                state.tx_waker.wake();
+        if ctrl.tcie().is_enabled() && regs.stat().read().tc().is_complete() {
+            state.tx_done.store(true, Ordering::Release);
+            state.tx_waker.wake();
 
-                // Disable TC interrupt
-                cortex_m::interrupt::free(|_| {
-                    regs.ctrl().modify(|_, w| w.tcie().disabled());
-                });
-            }
+            // Disable TC interrupt
+            cortex_m::interrupt::free(|_| {
+                regs.ctrl().modify(|_, w| w.tcie().disabled());
+            });
         }
     }
 }
diff --git a/src/lpuart/mod.rs b/src/lpuart/mod.rs
index bed10bdb0..35b531421 100644
--- a/src/lpuart/mod.rs
+++ b/src/lpuart/mod.rs
@@ -105,8 +105,9 @@ mod gpio {
 
                 impl GpioPin for super::lib::peripherals::$pin {}
 
-                impl Into<AnyPin> for super::lib::peripherals::$pin {
-                    fn into(self) -> AnyPin {
+                impl From<super::lib::peripherals::$pin> for AnyPin {
+                    // TODO: AJM: any reason we aren't using $pin?
+                    fn from(_val: super::lib::peripherals::$pin) -> Self {
                         AnyPin
                     }
                 }
@@ -242,7 +243,7 @@ pub fn configure_baudrate(regs: Regs, baudrate_bps: u32, clock: Clock) -> Result
     // Configure BAUD register
     regs.baud().modify(|_, w| unsafe {
         // Clear and set OSR
-        w.osr().bits((osr - 1) as u8);
+        w.osr().bits(osr - 1);
         // Clear and set SBR
         w.sbr().bits(sbr);
         // Set BOTHEDGE if OSR is between 4 and 7
@@ -305,9 +306,9 @@ pub fn configure_fifo(regs: Regs, config: &Config) {
     // Configure WATER register for FIFO watermarks
     regs.water().write(|w| unsafe {
         w.rxwater()
-            .bits(config.rx_fifo_watermark as u8)
+            .bits(config.rx_fifo_watermark)
             .txwater()
-            .bits(config.tx_fifo_watermark as u8)
+            .bits(config.tx_fifo_watermark)
     });
 
     // Enable TX/RX FIFOs
@@ -377,7 +378,7 @@ pub fn calculate_baudrate(baudrate: u32, src_clock_hz: u32) -> Result<(u8, u16)>
     // Try OSR values from 4 to 32
     for osr_temp in 4u8..=32u8 {
         // Calculate SBR: (srcClock_Hz * 2 / (baudRate * osr) + 1) / 2
-        let sbr_calc = ((src_clock_hz * 2) / (baudrate * osr_temp as u32) + 1) / 2;
+        let sbr_calc = ((src_clock_hz * 2) / (baudrate * osr_temp as u32)).div_ceil(2);
 
         let sbr_temp = if sbr_calc == 0 {
             1
@@ -390,11 +391,7 @@ pub fn calculate_baudrate(baudrate: u32, src_clock_hz: u32) -> Result<(u8, u16)>
         // Calculate actual baud rate
         let calculated_baud = src_clock_hz / (osr_temp as u32 * sbr_temp as u32);
 
-        let temp_diff = if calculated_baud > baudrate {
-            calculated_baud - baudrate
-        } else {
-            baudrate - calculated_baud
-        };
+        let temp_diff = calculated_baud.abs_diff(baudrate);
 
         if temp_diff <= baud_diff {
             baud_diff = temp_diff;
diff --git a/src/ostimer.rs b/src/ostimer.rs
index a4cab6970..8bc68389a 100644
--- a/src/ostimer.rs
+++ b/src/ostimer.rs
@@ -151,6 +151,12 @@ pub struct Alarm<'d> {
     _phantom: core::marker::PhantomData<&'d mut ()>,
 }
 
+impl<'d> Default for Alarm<'d> {
+    fn default() -> Self {
+        Self::new()
+    }
+}
+
 impl<'d> Alarm<'d> {
     /// Create a new alarm instance
     pub fn new() -> Self {
diff --git a/src/rtc.rs b/src/rtc.rs
index d62da1f0a..facb9cf8c 100644
--- a/src/rtc.rs
+++ b/src/rtc.rs
@@ -102,25 +102,36 @@ pub fn convert_seconds_to_datetime(seconds: u32) -> RtcDateTime {
         days -= days_in_year;
         year += 1;
 
-        days_in_year = if year % 4 == 0 {
+        days_in_year = if year.is_multiple_of(4) {
             DAYS_IN_A_YEAR + 1
         } else {
             DAYS_IN_A_YEAR
         };
     }
 
-    let mut days_per_month = [0u8, 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31];
-    if year % 4 == 0 {
-        days_per_month[2] = 29;
-    }
+    let days_per_month = [
+        31,
+        if year.is_multiple_of(4) { 29 } else { 28 },
+        31,
+        30,
+        31,
+        30,
+        31,
+        31,
+        30,
+        31,
+        30,
+        31,
+    ];
 
     let mut month = 1;
-    for m in 1..=12 {
-        if days <= days_per_month[m] as u32 {
+    for (m, month_days) in days_per_month.iter().enumerate() {
+        let m = m + 1;
+        if days <= *month_days as u32 {
             month = m;
             break;
         } else {
-            days -= days_per_month[m] as u32;
+            days -= *month_days as u32;
         }
     }
 
diff --git a/src/uart.rs b/src/uart.rs
index 3209a318d..3705959d3 100644
--- a/src/uart.rs
+++ b/src/uart.rs
@@ -1,6 +1,10 @@
 //! Minimal polling UART2 bring-up replicating MCUXpresso hello_world ordering.
 //! WARNING: This is a narrow implementation only for debug console (115200 8N1).
 
+// TODO(AJM): As of 2025-11-13, we need to do a pass to ensure safety docs
+// are complete prior to release.
+#![allow(clippy::missing_safety_doc)]
+
 use core::cell::RefCell;
 
 use cortex_m::interrupt::Mutex;
@@ -118,7 +122,7 @@ impl<I: Instance> Uart<I> {
                 StopBits::Two => w.sbns().two(),
             };
             // OSR field encodes (osr-1); use raw bits to avoid a long match on all variants
-            let raw_osr = osr.saturating_sub(1) as u8;
+            let raw_osr = osr.saturating_sub(1);
             unsafe { w.osr().bits(raw_osr).sbr().bits(sbr) }
         });
         // 3) CTRL baseline and parity
@@ -195,6 +199,12 @@ pub struct RingBuffer {
     count: usize,
 }
 
+impl Default for RingBuffer {
+    fn default() -> Self {
+        Self::new()
+    }
+}
+
 impl RingBuffer {
     pub const fn new() -> Self {
         Self {