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authorDaniel Bevenius <[email protected]>2022-09-12 11:44:21 +0200
committerDaniel Bevenius <[email protected]>2022-09-12 11:49:09 +0200
commitbe20512f17210ae179078c4bb082211d00d828da (patch)
tree98c0691aac43474c6179701a4b7f94fe42ee3f0c /src
parenta19bcb69d1eeeb2c7192bffce60dbefe1e0df28b (diff)
Add contants and update comment about ALP
This commit add two constants and updates the comment about ALP. It was not easy to find the definition of ALP but after searching I found what I believe is the correct definition in section 3.3 "Clocks" in the referenced document below. Active Low Power (ALP): Supplied by an internal or external oscillator. This clock is requested by cores when accessing backplane registers in other cores or when performing minor computations. When an external crystal is used to provide reference clock, ALP clock frequency is determined by the frequency of the external oscillator. A 37.4 MHz reference clock is recommended. Refs: https://www.infineon.com/dgdl/Infineon-AN214828_Power_Consumption_Measurements-ApplicationNotes-v03_00-EN.pdf?fileId=8ac78c8c7cdc391c017d0d2803a4630d
Diffstat (limited to 'src')
-rw-r--r--src/lib.rs10
1 files changed, 7 insertions, 3 deletions
diff --git a/src/lib.rs b/src/lib.rs
index e145b821b..8e43f51f1 100644
--- a/src/lib.rs
+++ b/src/lib.rs
@@ -92,6 +92,9 @@ const BACKPLANE_WINDOW_SIZE: usize = 0x8000;
92const BACKPLANE_ADDRESS_MASK: u32 = 0x7FFF; 92const BACKPLANE_ADDRESS_MASK: u32 = 0x7FFF;
93const BACKPLANE_ADDRESS_32BIT_FLAG: u32 = 0x08000; 93const BACKPLANE_ADDRESS_32BIT_FLAG: u32 = 0x08000;
94const BACKPLANE_MAX_TRANSFER_SIZE: usize = 64; 94const BACKPLANE_MAX_TRANSFER_SIZE: usize = 64;
95// Active Low Power (ALP) clock constants
96const BACKPLANE_ALP_AVAIL_REQ: u8 = 0x08;
97const BACKPLANE_ALP_AVAIL: u8 = 0x40;
95 98
96// Broadcom AMBA (Advanced Microcontroller Bus Architecture) Interconnect (AI) 99// Broadcom AMBA (Advanced Microcontroller Bus Architecture) Interconnect (AI)
97// constants 100// constants
@@ -603,10 +606,11 @@ where
603 // seems to break backplane??? eat the 4-byte delay instead, that's what the vendor drivers do... 606 // seems to break backplane??? eat the 4-byte delay instead, that's what the vendor drivers do...
604 //self.write32(FUNC_BUS, REG_BUS_RESP_DELAY, 0).await; 607 //self.write32(FUNC_BUS, REG_BUS_RESP_DELAY, 0).await;
605 608
606 // Init ALP (no idea what that stands for) clock 609 // Init ALP (Active Low Power) clock
607 self.write8(FUNC_BACKPLANE, REG_BACKPLANE_CHIP_CLOCK_CSR, 0x08).await; 610 self.write8(FUNC_BACKPLANE, REG_BACKPLANE_CHIP_CLOCK_CSR, BACKPLANE_ALP_AVAIL_REQ)
611 .await;
608 info!("waiting for clock..."); 612 info!("waiting for clock...");
609 while self.read8(FUNC_BACKPLANE, REG_BACKPLANE_CHIP_CLOCK_CSR).await & 0x40 == 0 {} 613 while self.read8(FUNC_BACKPLANE, REG_BACKPLANE_CHIP_CLOCK_CSR).await & BACKPLANE_ALP_AVAIL == 0 {}
610 info!("clock ok"); 614 info!("clock ok");
611 615
612 let chip_id = self.bp_read16(0x1800_0000).await; 616 let chip_id = self.bp_read16(0x1800_0000).await;