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authorRoy Buitenhuis <[email protected]>2023-04-11 16:53:04 +0200
committerRoy Buitenhuis <[email protected]>2023-04-11 16:53:04 +0200
commit00258bca4320bcf33f6285126a1f31fd6a9ed83c (patch)
tree9209112db9eefb110c325f3ca9c421357eefc0c4 /tests/riscv32/memory.x
parent813bba200f1a068a47bc6d9eafc74a190ffb0316 (diff)
Add empty test binary for riscv
Diffstat (limited to 'tests/riscv32/memory.x')
-rw-r--r--tests/riscv32/memory.x14
1 files changed, 14 insertions, 0 deletions
diff --git a/tests/riscv32/memory.x b/tests/riscv32/memory.x
new file mode 100644
index 000000000..316d577d4
--- /dev/null
+++ b/tests/riscv32/memory.x
@@ -0,0 +1,14 @@
1MEMORY
2{
3 ROM : ORIGIN = 0x80000000, LENGTH = 0x00020000
4 RAM : ORIGIN = 0x84000000, LENGTH = 0x00008000
5}
6
7REGION_ALIAS("REGION_TEXT", ROM);
8REGION_ALIAS("REGION_RODATA", ROM);
9REGION_ALIAS("REGION_DATA", RAM);
10REGION_ALIAS("REGION_BSS", RAM);
11REGION_ALIAS("REGION_HEAP", RAM);
12REGION_ALIAS("REGION_STACK", RAM);
13
14_stack_start = ORIGIN(RAM) + LENGTH(RAM) - 4;